Digital Electronics - Practical Electronics for Inventors, Fourth Edition - Paul Scherz, Simon Monk

Practical Electronics for Inventors, Fourth Edition - Paul Scherz, Simon Monk (2016)

Chapter 12. Digital Electronics

Before beginning, we must warn you that there is a lot of information in this chapter, and it may be difficult to absorb all this at once. Some information is present largely for historical interest and to provide a better understanding of how complex digital systems such as microcontrollers work. Our advice is to skim to your heart’s content, and pull out whatever information you find practical. The basic principles are still the same, but if you find that your design uses more than three ICs, you probably could be using a microcontroller (the subject of Chap. 13).

12.1 The Basics of Digital Electronics

Until now, we have mainly covered the analog realm of electronics—circuits that accept and respond to voltages that vary continuously over a given range. Such analog circuits included rectifiers, filters, amplifiers, simple RC timers, oscillators, simple transistor switches, and so on. Although each of these analog circuits is fundamentally important in its own right, these circuits lack an important feature: they cannot store and process bits of information needed to make complex logical decisions. To incorporate logical decision-making processes into a circuit, you need to use digital electronics.

This chapter is concerned with laying the foundations of digital electronics. The actual implementation of digital electronics these days is either handled by microcontrollers (see Chap. 13) or programmable logic devices (see Chap. 14).



12.1.1 Digital Logic States

In digital electronics, there are only two voltage states present at any point within a circuit. These voltage states are either high or low. The voltage being high or low at a particular location within a circuit can signify a number of things. For example, it may represent the on or off state of a switch or saturated transistor, one bit of a number, whether an event has occurred, or whether some action should be taken.

The high and low states can be represented as true and false statements, which are used in Boolean logic. In most cases, high equals true and low equals false. However, this does not need to be the case—you could make high equal to false and low equal to true. The decision to use one convention over the other is a matter left ultimately to the designer. In digital lingo, to avoid people getting confused over which convention is in use, the term positive true logic is used when high equals true, while the term negative true logic is used when high equals false.

In Boolean logic, the symbols 1 and 0 are used to represent true and false, respectively. Now, unfortunately, 1 and 0 are also used in electronics to represent high and low voltage states, where high equals 1 and low equals 0. As you can see, things can get a bit confusing, especially if you are not sure which type of logic convention is being used: positive true or negative true logic. In Sec. 12.3, you will see some examples that deal with this confusing issue.

The exact voltages assigned to high or low voltage states depend on the specific logic IC that is used (as it turns out, digital components are IC-based). As a general rule of thumb, +5 V is considered high, while 0 V (ground) is considered low. However, as you will see in Sec. 12.4, this does not need to be the case. For example, some logic ICs may interpret a voltage from +2.4 to +5 V as high and a voltage from +0.8 to 0 V as low. Other ICs may use an entirely different range.

12.1.2 Number Codes Used in Digital Electronics


Because digital circuits work with only two voltage states, it is logical to use the binary number system to keep track of information. A binary number is composed of two binary digits, 0 and 1, which are also called bits (for example, 0 = low voltage and 1 = high voltage). By contrast, a decimal number such as 736 is represented by successive powers of 10:

73610 = 7 × 102 + 3 × 101 + 6 × 100

Similarly, a binary number such as 11100 (2810) can be expressed as successive powers of 2:

111002 = 1 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20

The subscript tells which number system is in use (X10 = decimal number and X2 = binary number). The highest-order bit (leftmost bit) is called the most significant bit (MSB), while the lowest-order bit (rightmost bit) is called the least significant bit (LSB). Methods used to convert from decimal to binary and vice versa are shown in Fig. 12.2.



It should be noted that most digital systems deal with 4, 8, 16, or 32 bits at a time. The decimal-to-binary conversion example given here has a 7-bit answer. In an 8-bit system, you would need to put an additional 0 in front of the MSB (for example, 01101101). In a 16-bit system, nine additional 0s would need to be added (for example, 0000000001101101).

As a practical note, the easiest way to convert a number from one base to another is to use a calculator. For example, to convert a decimal number into a binary number, type in the decimal number (in base 10 mode) and then change to binary mode (which usually entails a second function key). The number will now be in binary (1s and 0s). To convert a binary number to a decimal number, start out in binary mode, type in the number, and then switch to decimal mode.

Octal and Hexadecimal

Two other number systems used in digital electronics include the octal and hexadecimal systems. In the octal system (base 8), there are 8 allowable digits: 0, 1, 2, 3, 4, 5, 6, and 7. In the hexadecimal system (base 16), there are 16 allowable digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Here are examples of octal and hexadecimal numbers with decimal equivalents:

2478 (octal) = 2 × 82 + 4 × 81 + 7 × 80 = 16710 (decimal)

2D516 (hex) = 2 × 162 + D (=1310) × 161 + 9 × 160 = 72510 (decimal)

Of course, binary numbers are the natural choice for digital systems, but since these binary numbers can become long and difficult to interpret by our decimal-based brains (a result of our ten fingers), it is common to write them out in hexadecimal or octal form.

Unlike decimal numbers, octal and hexadecimal numbers can be translated easily to and from binary. This is because a binary number, no matter how long, can be broken up into 3-bit groupings (for octal) or 4-bit groupings (for hexadecimal). You simply add zero to the beginning of the binary number if the total numbers of bits is not divisible by 3 or 4. Figure 12.3 should paint the picture better than words.



Today, the hexadecimal system has essentially replaced the octal system. The octal system was popular at one time, when microprocessor systems used 12-bit and 36-bit words, along with a 6-bit alphanumeric code, which are all divisible by 3-bit units (1 octal digit). Today, microprocessor systems mainly work with 8-bit, 16-bit, 20-bit, 32-bit, or 64-bit words, which are all divisible by 4-bit units (1 hex digit). In other words, an 8-bit word can be broken down into 2 hex digits, a 16-bit word into 4 hex digits, a 20-bit word into 5 hex digits, and so on.

Hexadecimal representation of binary numbers pops up in many memory and microprocessor applications that use programming codes (for example, within assembly language) to address memory locations and initiate other specialized tasks that would otherwise require typing in long binary numbers. For example, a 20-bit address code used to identify one of a million memory locations can be replaced with a hexadecimal code (in the assembly program) that reduces the count to five hex digits. Note that a compiler program later converts the hex numbers within the assembly language program into binary numbers (machine code), which the microprocessor can use. Table 12.1 shows a conversion table.

TABLE 12.1 Decimal, Binary, Octal, Hex, BCD Conversion Table







0000 0000



0000 0000


0000 0001



0000 0001


0000 0010



0000 0010


0000 0011



0000 0011


0000 0100



0000 0100


0000 0101



0000 0101


0000 0110



0000 0110


0000 0111



0000 0111


0000 1000



0000 1000


0000 1001



0000 1001


0000 1010



0001 0000


0000 1011



0001 0001


0000 1100



0001 0010


0000 1101



0001 0011


0000 1110



0001 0100


0000 1111



0001 0101


0001 0000



0001 0110


0001 0001



0001 0111


0001 0010



0001 1000


0001 0011



0001 1001


0001 0100



0010 0000

Binary-Coded Decimal

Binary-coded decimal (BCD) is used to represent each digit of a decimal number as a 4-bit binary number. For example, the number 15010 in BCD is expressed as follows:

To convert from BCD to binary is vastly more difficult, as shown in Fig. 12.4. Of course, you could cheat by converting the BCD into decimal first and then convert to binary, but that does not show you the mechanics of how machines do things with 1s and 0s. You will rarely need to do BCD-to-binary conversion, so we will not dwell on this topic.



BCD is commonly used when outputting to decimal (0-9) displays, such as those found in digital clocks and multimeters. BCD will be discussed in Sec. 12.3.

Sign-Magnitude and 2’s Complement Numbers

Up to now, we have not considered negative binary numbers. How do you represent them? A simple method is to use sign-magnitude representation. In this method, you simply reserve a bit, usually the MSB, to act as a sign bit. If the sign bit is 0, the number is positive; if the sign bit is 1, the number is negative (see Fig. 12.5).



Although the sign-magnitude representation is simple, it is seldom used, because adding requires a different procedure than subtracting (as you will see in the next section). Occasionally, you will see sign-magnitude numbers used in display and analog-to-digital applications, but you will hardly ever see them in circuits that perform arithmetic.

A more popular choice when dealing with negative numbers is to use 2’s complement representation. In 2’s complement, the positive numbers are exactly the same as unsigned binary numbers. A negative number, however, is represented by a binary number, which when added to its corresponding positive equivalent results in zero. In this way, you can avoid two separate procedures for doing addition and subtraction. You will see how this works in the next section. A simple procedure outlining how to convert a decimal number into a binary number and then into a 2’s complement number, and vice versa, is outlined in Fig. 12.5.

Decimal, Sign-Magnitude, 2’s Complement Conversion Table





0000 0111

0000 0111


0000 0110

0000 0110


0000 0101

0000 0101


0000 0100

0000 0100


0000 0011

0000 0011


0000 0010

0000 0010


0000 0001

0000 0001


0000 0000

0000 0000


1000 0001

1111 1111


1000 0010

1111 1110


1000 0011

1111 1101


1000 0100

1111 1100


1000 0101

1111 1011


1000 0110

1111 1010


1000 0111

1111 1001


1000 1000

1111 1000

Arithmetic with Binary Numbers

Adding, subtracting, multiplying, and dividing binary numbers, hexadecimal numbers, and other representations can be done with a calculator set to that particular base mode. But that’s cheating, and it doesn’t help you understand the mechanics of how it is done. The mechanics become important when designing the actual arithmetical circuits. Here are the basic techniques used to add and subtract binary numbers.




Adding binary numbers is just like adding decimal numbers. Whenever the result of adding one column of numbers is greater than one digit, a 1 is carried over to the next column to be added.




Subtracting binary numbers is not as easy as it looks. It is similar to decimal subtraction but can be confusing. For example, you might think that if you were to subtract a 1 from a 0, you would borrow a 1 from the column to the left. No! You must borrow a 10 (210). It becomes a headache if you try to do this by hand. The trick to subtracting binary numbers is to use the 2’s complement representation that provides the sign bit, and then just add the positive number with the negative number to get the sum. This method is often used by digital circuits because it allows both addition and subtraction, without the headache of needing to subtract the smaller number from the larger number.


American Standard Code for Information Interchange (ASCII) is an alphanumeric code used to transmit letters, symbols, numbers, and special nonprinting characters between computers and computer peripherals (such as printers and keyboards). ASCII consists of 128 different 7-bit codes.

Codes from 000 0000 (or hex 00) to 001 1111 (or hex 1F) are reserved for nonprinting characters or special machine commands like ESC (escape), DEL (delete), CR (carriage return), and LF (line feed). Codes from 010 0000 (or hex 20) to 111 1111 (or hex 7F) are reserved for printing characters like a, A, #, &, {, @, and 3. Tables 12.2 and 12.3 show the ASCII nonprinting and printing characters.

TABLE 12.2 ASCII Nonprinting Characters









000 0000






000 0001



Start of heading



000 0010



Start of text



000 0011



End of text



000 0100



End of transmit



000 0101






000 0110






000 0111






000 1000






000 1001



Horizontal tab



000 1010



Line feed



000 1011



Vertical tab



000 1100



Form feed



000 1101



Carriage return



000 1110



Shift out



000 1111



Shift in



001 0000



Data line escape



001 0001



Device control 1



001 0010



Device control 2



001 0011



Device control 3



001 0100



Device control 4



001 0101



Neg acknowledge



001 0110



Synchronous idle



001 0111



End of transmit block



001 1000






001 1001



End of medium



001 1010






001 1011






001 1100



File separator



001 1101



Group separator



001 1110



Record separator



001 1111



Unit separator

TABLE 12.3 ASCII Printing Characters







010 0000




010 0001




010 0010



010 0011




010 0100




010 0101




010 0110




010 0111



010 1000




010 1001




010 1010




010 1011




010 1100




010 1101




010 1110




010 1111




011 0000




011 0001




011 0010




011 0011




011 0100




011 0101




011 0110




011 0111




011 1000




011 1001




011 1010




011 1011




011 1100




011 1101




011 1110




011 1111




100 0000




100 0001




100 0010




100 0011




100 0100




100 0101




100 0110




100 0111




100 1000




100 1001




100 1010




100 1011




100 1100




100 1101




100 1110




100 1111




101 0000




101 0001




101 0010




101 0011




101 0100




101 0101




101 0110




101 0111




101 1000




101 1001




101 1010




101 1011




101 1100




101 1101




101 1110




101 1111




110 0000



110 0001




110 0010




110 0011




110 0100




110 0101




110 0110




110 0111




110 1000




110 1001




110 1010




110 1011




110 1100




110 1101




110 1110




110 1111




111 0000




111 0001




111 0010




111 0011




111 0100




111 0101




111 0110




111 0111




111 1000




111 1001




111 1010




111 1011




111 1100




111 1101




111 1110



111 1111


In practice, when ASCII code is sent, an additional bit is added to make it compatible with 8-bit systems. This bit may be set to 0 and ignored, it may be used as a parity bit for error detection (Sec. 12.3.8 covers parity bits), or it may act as a special function bit used to implement an additional set of specialized characters.

12.1.3 Clock Timing and Parallel versus Serial Transmission

Before moving on to the next section, let’s take a brief look at three important items: clock timing, parallel transmission, and serial transmission.

Clock Timing



Most digital circuits require precise timing to function properly. Usually, a clock circuit that generates a series of high and low pulses at a fixed frequency is used as a reference on which to base all critical actions executed within a system. The clock is also used to push bits of data through the digital circuitry. The period of a clock pulse is related to its frequency by T = 1/f. So, if T = 10 ns, then f = 1/(10 ns) = 100 MHz.

Serial versus Parallel Representation

Binary information can be transmitted from one location to another in either a serial or parallel manner. The serial format uses a single electrical conductor (and a common ground) for data transfer. Each bit from the binary number occupies a separate clock period, with the change from one bit to another occurring at each falling or leading clock edge; the type of edge depends on the circuitry used.

Figure 12.9 shows an 8-bit (10110010) word that is transmitted from circuit A to circuit B in 8 clock pulses (0-7). In computer systems, serial communications are used to transfer data between keyboard and computer, as well as to transfer data between two computers via a telephone line.



Parallel transmission uses separate electrical conductors for each bit (and a common ground). In Fig. 12.9, an 8-bit string (01110110) is sent from circuit A to circuit B. As you can see, unlike serial transmission, the entire word is transmitted in only one clock cycle, not eight clock cycles. In other words, it is eight times faster. Parallel communications are most frequently found within microprocessor systems that use multiline data and control buses to transmit data and control instructions from the microprocessor to other microprocessor-based devices (such as memory and output registers).

12.2 Logic Gates

Logic gates are the building blocks of digital electronics. The fundamental logic gates include the INVERT (NOT), AND, NAND, OR, NOR, exclusive OR (XOR), and exclusive NOR (XNOR) gates. Each of these gates performs a different logical operation. Figure 12.10 provides a description of what each logic gate does and gives a switch and transistor analogy for each gate.


FIGURE 12.10

12.2.1 Multiple-Input Logic Gates

AND, NAND, OR, and NOR gates often come with more than two inputs (this is not the case with XOR and XNOR gates, which require two inputs only). Figure 12.11 shows a four-input AND, an eight-input AND, a three-input OR, and an eight-input OR gate. With the eight-input AND gate, all inputs must be high for the output to be high. With the eight-input OR gate, at least one of the inputs must be high for the output to go high.


FIGURE 12.11

12.2.2 Digital Logic Gate ICs

As we mentioned in the introduction to this chapter, the use of individual logic ICs has almost completely been superseded by the use of microcontrollers, the programmable logic devices such as field-programmable gate arrays (FPGAs). However, one or two logic ICs are still often used together in simple applications.

There are a number of technologies used in the fabrication of digital logic. The most popular technology is complementary MOSFET (CMOS) logic.

A logic IC typically houses more than one logic gate (for example, a quad two-input NAND, hex inverter, and so on). Each of the gates within the IC shares a common supply voltage that is implemented via two supply pins: a positive supply pin (+VCC or +VDD) and a ground pin (GND). The most popular “HC” range of digital logic gate ICs will operate from a supply of 2-6 V with 5 V being something of a standard operating voltage as a relic from the age of transistor-transistor logic (TTL).

Generally speaking, input and output voltage levels are assumed to be 0 V (low) and +5 V (high). However, the actual input voltage required and the actual output voltage provided by the gate are not set in stone. For example, the 74HCxx series will recognize a high input from 2.5 to 5 V and a low from 0 to 2.1 V. However, for the CMOS 4000B series (VCC = +5 V), recognizable input voltages range from 3.3 to 5 V for high and 0 to 1.7 V for low. Guaranteed high and low output levels range from 4.9 to 5 V and 0 to 0.1 V, respectively. Again, we will discuss specifics later in Sec. 12.4. For now, let’s just get acquainted with what some of these ICs look like, as shown in Figs. 12.12 and 12.13. The CMOS devices listed in the figures include 74HCxx and 4000(B). The TTL devices shown include the 74xx, 74Fxx, and 74LS.


FIGURE 12.12


FIGURE 12.13

12.2.3 Applications for a Single Logic Gate

Before we jump into the heart of logic gate applications that involve combining logic gates to form complex decision-making circuits, let’s take a look at a few simple applications that require the use of a single logic gate.

Enable/Disable Control

An enable/disable gate is a logic gate that acts to control the passage of a given waveform. The waveform—say, a clock signal—is applied to one of the gate’s inputs, while the other input acts as the enable/disable control lead. Enable/disable gates are used frequently in digital systems to enable and disable control information from reaching various devices. Figure 12.14 shows two enable/disable circuits: the first uses an AND gate, and the second uses an OR gate. NAND and NOR gates are also frequently used as enable gates.


FIGURE 12.14

In the upper part of the figure, an AND gate acts as the enable gate. When the input enable lead is made high, the clock signal will pass to the output. In this example, the input enable is held high for 4 µs, allowing 4 clock pulses (where Tclk = 1 µs) to pass. When the input enable lead is low, the gate is disabled, and no clock pulses make it through to the output.

Below, an OR gate is used as the enable gate. The output is held high when the input enable lead is high, even as the clock signal is varying. However, when the enable input is low, the clock pulses are passed to the output.

Waveform Generation

By using the basic enable/disable function of a logic gate, as illustrated in the previous example, it is possible, with the help of a repetitive waveform generator circuit, to create specialized waveforms that can be used for the digital control of sequencing circuits.

An example waveform generator circuit is the Johnson counter. The Johnson counter will be discussed in Sec. 12.8. For now, let’s simply focus on the outputs. In Fig. 12.15, a Johnson counter uses clock pulses to generate different output waveforms, as shown in the timing diagram. Outputs A, B, C, and D go high for 4 µs (four clock periods) and are offset from each other by 1 µs. Outputs and produce waveforms that are complements of outputs A, B, C, and D, respectively.


FIGURE 12.15

Now, there may be certain applications that require 4-µs high/low pulses applied at a given time, as the counter provides. However, what would you do if the application requires a 3-µs high waveform that begins at 2 µs and ends at 5 µs (relative to the time scale indicated in Fig. 12.15)? This is where the logic gates come in handy. For example, if you attach an AND gate’s inputs to the counter’s A and B outputs, you will get the desired 2- to 5-µs high waveform at the AND gate’s output: from 1 to 2 µs the AND gate outputs a low (A = 1, B = 0), from 2 to 5 µs the AND gate outputs a high (A = 1, B = 1), and from 5 to 6 µs the AND gate outputs a low (A = 0, B = 1). See the leftmost area of Fig. 12.16.


FIGURE 12.16

Various other specialized waveforms can be generated by using different logic gates and tapping different outputs of the Johnson shift counter. In Fig. 12.16, six other possibilities are shown.

12.2.4 Combinational Logic

Combinational logic involves combining logic gates together to form circuits capable of enacting more useful, complex functions. For example, let’s design the logic used to instruct a janitor-type robot to recharge itself (seek out a power outlet) only when a specific set of conditions is met. The “recharge itself” condition is specified as follows:

Either its battery is low (indicated by a high output signal from a battery-monitor circuit)


The workday is over (indicated by a high output signal from a timer circuit)]


[When vacuuming is complete (indicated by a high voltage output from a vacuum-completion monitor circuit)


When waxing is complete (indicated by a high output signal from a wax-completion monitor circuit)]

Let’s also assume that the power-outlet-seeking routine circuit is activated when a high is applied to its input.

Two simple combinational circuits that perform the desired logic function for the robot are shown in Fig. 12.17. The two circuits use a different number of gates but perform the same function. Now, the question remains, how did we come up with these circuits? In either circuit, it is not hard to predict which gates are needed. You simply exchange the word and present within the conditional statement with an AND gate within the logic circuit, and exchange the word or present within the conditional statement with an OR gate within the logic circuit. Common sense takes care of the rest.


FIGURE 12.17

However, when you begin designing more complex circuits, using intuition to figure out what kind of logic gates to use and how to join them together becomes exceedingly difficult. To make designing combinational circuits easier, a special symbolic language called Boolean algebra is used, which uses only true and false variables. A Boolean expression for the robot circuit would appear as follows:

E = (B + T) + VW

This expression amounts to saying that if B (battery-check circuit’s output) or T (timer circuit’s output) is true, or V and W (vacuum and waxing circuit outputs) are true, then E (enact power-outlet circuit input) is true.

Note that the word or is replaced by the symbol +, and the word and is simply expressed in a way similar to multiplying two variables together (placing them side by side or using a dot between variables). Also note that the term true in Boolean algebra is expressed as a 1, and false is expressed as a 0. Here, we are assuming positive logic, where true equals high voltage. Using the Boolean expression for the robot circuit, we can come up with some of the following results (the truth table in Fig. 12.17 provides all possible results):

E = (B + T) + VW

E = (1 + 1) + (1 · 1) = 1 + 1 = 1

(battery is low, time to sleep, finished with chores = go recharge)

E = (1 + 0) + (0 · 0) = 1 + 0 = 1

(battery is low = go recharge)

E = (0 + 0) + (1 · 0) = 0 + 0 = 0

(hasn’t finished waxing = don’t recharge yet)

E = (0 + 0) + (1 · 1) = 0 + 1 = 1

(has finished all chores = go recharge)

E = (0 + 0) + (0 · 0) = 0 + 0 = 0

(hasn’t finished vacuuming and waxing = don’t recharge yet)

The robot example showed you how to express AND and OR functions in Boolean algebraic terms. But what about the negation operations (NOT, NAND, and NOR) and the exclusive operations (XOR and XNOR)? How do you express these in Boolean terms?

· For a NOT condition, place a line over the NOT’ed variable or variables.

· For a NAND expression, place a line over an AND expression.

· For a NOR expression, place a line over an OR expression.

· For exclusive operations, use the symbol ⊕.

Figure 12.18 shows a rundown of all the possible Boolean expressions for the various logic gates.


FIGURE 12.18

Like conventional algebra, Boolean algebra has a set of logic identities that can be used to simplify the Boolean expressions and thus make circuits more compact. These identities go by names such as the commutative law of addition, associate law of addition, and distributive law. Instead of worrying about what the various identities are called, simply make reference to the list of identities provided on the next page. Most of these identities are self-explanatory, although a few are not so obvious, as you will see in a minute. The various circuits in Fig. 12.19 show some of the identities in action.


FIGURE 12.19


Let’s find the initial Boolean expression for the circuit in Fig. 12.20, and then use the logic identities to come up with a circuit that requires fewer gates.


FIGURE 12.20

The circuit shown here is expressed by the following Boolean expression:

This expression can be simplified by using Identity 5:

This makes:

Using Identities 17 and 11 you get:

Factoring a from the preceding term gives:

Using Identity 12, you get:

Finally, using Identity 21, you get the simplified expression:

Notice that A is now missing. This means that the logic input at A has no effect on the output and therefore can be omitted. From the reduction, you get the simplified circuit in the bottom part of the figure.

Dealing with Exclusive Gates (Identities 22 and 23)

Now let’s take a look at a couple of not-so-obvious logic identities: those that involve the XOR (Identity 22) and XNOR (Identity 23) gates. The leftmost section in Fig. 12.21 shows equivalent circuits for the XOR gate. In the lower two equivalent circuits, Identity 22 is proved by Boolean reduction. Equivalent circuits for the XNOR gate are shown in the rightmost section of the figure. To prove Identity 23, you can simply invert Identity 22.


FIGURE 12.21

De Morgan’s Theorem (Identities 18 and 19)

To simplify circuits containing NANDs and NORs, you can use an incredibly useful theorem known as De Morgan’s theorem. This theorem allows you to convert an expression having an inversion bar over two or more variables into an expression having inversion bars over single variables only. De Morgan’s theorem (Identities 18 and 19) is as follows:

The easiest way to prove that these identities are correct is to use Fig. 12.22, noting that the truth tables for the equivalent circuits are the same. Note the inversion bubbles present on the inputs of the corresponding leftmost gates. The inversion bubbles mean that before inputs A and B are applied to the base gate, they are inverted (negated). In other words, the bubbles are simplified expressions for NOT gates.


FIGURE 12.22

Why do you use the inverted-input OR gate symbol instead of a NAND gate symbol? Or why would you use the inverted-input AND gate symbol instead of a NOR gate symbol? This is left up to the designer to choose whatever symbol seems most logical to use. For example, when designing a circuit, it may be easier to think about ORing or ANDing inverted inputs than to think about NANDing or NORing inputs. Similarly, it may be easier to create truth tables or work with Boolean expressions using the inverted-input gate. It is typically easier to create truth tables and Boolean expressions that do not have variables joined under a common inversion bar. Of course, when it comes time to construct the actual working circuit, you probably will want to convert to the NAND and NOR gates because they do not require additional NOT gates at their inputs.

Bubble Pushing

A shortcut method for forming equivalent logic circuits, based on De Morgan’s theorem, is to use what’s called bubble pushing.

Bubble pushing involves the following tricks:

· Change an AND gate to an OR gate or change an OR gate to an AND gate.

· Add inversion bubbles to the inputs and outputs where there were none, while removing the original bubbles.

That’s it. You can prove to yourself that this works by examining the corresponding truth tables for the original gate and the bubble-pushed gate, or you can work out the Boolean expressions using De Morgan’s theorem. Figure 12.23 shows examples of bubble pushing.


FIGURE 12.23

Universal Capability of NAND and NOR Gates

NAND and NOR gates are referred to as universal gates because each alone can be combined together with itself to form all other possible logic gates. The ability to create any logic gate from NAND or NOR gates is obviously a handy feature. For example, if you do not have an XOR IC handy, you can use a single multigate NAND gate (such as 74HC00) instead. Figure 12.24 shows how to wire NAND or NOR gates together to create equivalent circuits of the various logic gates.


FIGURE 12.24


When a Boolean expression is reduced, the equation that is left over typically will be of one of the following two forms: product of sums (POS) or sum of products (SOP). A POS expression appears as two or more OR'ed variables AND'ed together with two or more additional OR'ed variables. An SOP expression appears as two or more AND'ed variables OR'ed together with additional AND'ed variables. Figure 12.25 shows two circuits that provide the same logic function (they are equivalent), but the circuit to the left is designed to yield a POS expression, while the circuit to the right is designed to yield a SOP expression.


FIGURE 12.25

Which circuit is best for design: the one that implements the POS expression or the one that implements the SOP expression? The POS design shown here would appear to be the better choice because it requires fewer gates. However, the SOP design is nice because it is easy to work with the Boolean expression. For example, which Boolean expression in Fig. 12.25 (POS or SOP) would you rather use to create a truth table? The SOP expression seems the obvious choice.

A more down-to-earth reason for using an SOP design has to do with the fact that special ICs called AND-OR-INVERTER (AOI) gates are designed to handle SOP expressions. For example, the 74LS54 AOI IC shown in Fig. 12.26 creates an inverted SOP expression at its output, via two two-input AND gates and two three-input AND gates NOR'ed together. A NOT gate can be attached to the output to get rid of the inversion bar, if desired. If specific inputs are not used, they should be held high, as shown in the example circuit in Fig. 12.26. AOI ICs come in many different configurations—check out the catalogs to see what’s available.


FIGURE 12.26

In Chap. 14 you will see how a combinational logic circuit like the ones described above can be programmed onto a special configurable chip called a field-programmable gate array (FPGA) without the need for large number of logic gate ICs.

12.2.5 Keeping Circuits Simple (Karnaugh Maps)

We have just covered how using the logic identities can simplify a Boolean expression. This is important because it reduces the number of gates needed to construct the logic circuit. However, as we are sure you will agree, having to work out Boolean problems in longhand is not easy. It takes time and ingenuity. A simple way to avoid the unpleasant task of using your ingenuity is to get a computer program that accepts a truth table or Boolean expression, and then provides you with the simplest expression, and perhaps even the circuit schematic.

However, let’s assume that you do not have such a program to help you out. Are you stuck with the Boolean longhand approach? No. You can use a technique referred to as Karnaugh mapping. With this technique, you take a given truth table (or Boolean expression that can be converted into a truth table), convert it into a Karnaugh map, apply some simple graphic rules, and come up with the simplest (most of the time) possible Boolean expression for your final circuit. Karnaugh mapping works best for circuits with three to four inputs—below this, things usually do not require much thought anyway; beyond four inputs, things get quite tricky.

Here’s a basic outline showing how to apply Karnaugh mapping to a three-input system:

1. Select a desired truth table. Let’s choose the one shown in Fig. 12.27. (If you have a Boolean expression, transform it into an SOP expression and use the SOP expression to create the truth table.)

2. Translate the truth table into a Karnaugh map. A Karnaugh map is similar to a truth table but has its variables represented along two axes. Translating the truth table into a Karnaugh map reduces the number of 1s and 0s needed to present the information. Figure 12.27 shows how the translation is carried out.

3. After you create the Karnaugh map, you can proceed to encircle adjacent cells of 1s into groups of 2, 4, 8, …, 2n. The more cells you can encircle in one grouping the simpler the final equation will be. You are not allowed to encircle 0s nor allowed to make diagonal loops. Every 1 must be in at least one group. Overlapping and wrapping around map are allowed.

4. Identify the variable that remain constant within each loop, and write out an SOP equation by OR’ing these variables together. Here, constant means that a variable and its inverse are not present together within the loop. For example, in Figure 12.27 section 3, the loop that contains four 1s is reduced to because B = 0 throughout the loop, while A and B aren’t constant because they take on values of 0 and 1 throughout that loop. (If a variable is constant 0, the final expression is the inverse of that variable; if the variable is constant 1 throughout the loop, the final expression is the non-inverted variable.)

5. The SOP expression you end up with is the simplest possible expression. With it, you can create your logic circuit. You may need to apply some bubble pushing to make the final circuit practical, as shown in Fig. 12.27.


FIGURE 12.27

To apply Karnaugh mapping to four-input circuits, you apply the same basic steps used in the three-input scheme. However, now you must use a 4 × 4 Karnaugh map to hold all the necessary information. Figure 12.28 shows an example of how a four-input truth table (or unsimplified fourvariable SOP expression) can be mapped and converted into a simplified SOP expression that can be used to create the final logic circuit.


FIGURE 12.28

Figure 12.29 shows and example that uses an AOI IC to implement the final SOP expression after mapping.


FIGURE 12.29

Other Looping Configurations

Figure 12.30 shows examples of other looping arrangements used with 4 × 4 Karnaugh maps.


FIGURE 12.30

If you want to make your life easier, try one of the free online Karnaugh mapping calculators. Do a Google search for “Karnaugh Map Explorer 2.0”. This tool will save you the hassle of having to draw maps and apply looping tricks yourself. You simply enter values into a truth table (or into the Karnaugh map) and the program calculates the final logical expression.

12.3 Combinational Devices

Now that you know a little something about how to use logic gates to enact functions represented within truth tables and Boolean expressions, it is time to take a look at some common functions that are used in the real world of digital electronics. As you will see, these functions are usually carried out by an IC that contains all the necessary logic.

As with almost everything discussed in this chapter, before using these ideas, you need to ask yourself if using a microcontroller would be more appropriate. However, many of the devices described here can be used with a microcontroller, especially when it comes to decoders. They can be a useful and low-cost solution for tasks such as driving more LEDs than there are pins on the microcontroller that you are using.

A word on IC part numbers before we begin. As with the logic gate ICs, the combinational ICs that follow will be of either the 4000 or 7400 series. It is important to note that an original TTL IC, like the 74138, is essentially the same device (usually with the same pinouts and function, but not always) as its newer counterparts, such as the 74F138, 74HC128 (CMOS), and 74LS138. The practical difference resides in the overall performance of the device (speed, power dissipation, voltage level rating, and so on). We will get into these gory details in a bit.


FIGURE 12.31

12.3.1 Multiplexers (Data Selectors) and Bilateral Switches

Multiplexers or data selectors act as digitally controlled switches. The term data selector appears to be the accepted term when the device is designed to act like an SPDT switch, while the term multiplexer is used when the throw count of the switch exceeds two, such as an SP8T. We will stick with this convention (although others may not).

A simple 1-of-2 data selector built from logic gates is shown in Fig. 12.32. The data select input of this circuit acts to control which input (A or B) gets passed to the output: When data select is low, input A passes while B is blocked. When data select is high, input B is passed while A is blocked. To understand how this circuit works, think of the AND gates as enable gates.


FIGURE 12.32

There are a number of different types of data selectors that come in IC form. For example, the 74LS157 quad 1-of-2 data selector IC, shown in Fig. 12.32, acts like an electrically controlled quad SPDT switch (or if you like, a 4PDT switch). When its select input is set high (1), inputs A1, A2, A3, and A4 are allowed to pass to outputs Q1, Q2, Q3, and Q4. When its select input is low (0), inputs B1, B2, B3, and B4 are allowed to pass to outputs Q1, Q2, Q3, and Q4. Either of these two conditions, however, ultimately depends on the state of the enable input.

When the enable input is low, all data-input signals are allowed to pass to the output; however, if the enable is high, the signals are not allowed to pass. This type of enable control is referred to as active-low enable, since the active function (passing the data to the output) occurs only with a low-level input voltage. The active-low input is denoted with a bubble (inversion bubble), and the outer label of the active-low input is represented with a line over it. Sometimes people omit the bubble and place a bar over the inner label. Both conventions are used commonly.

Figure 12.33 shows a 4-line-to-1-line multiplexer built with logic gates. This circuit resembles the 2-of-1 data selector shown in Fig. 12.32 but requires an additional select input to provide four address combinations.


FIGURE 12.33

In terms of ICs, there are multiplexers of various input line capacities. For example, the 74151 8-line-to-1-line multiplexer uses three select inputs (S0, S1, S2) to choose among one of eight possible data inputs (I0 to I7) to be funneled to the output. Note that this device actually has two outputs: one true (pin 5) and one inverted (pin 6). The active-low enable forces the true output low when set high, regardless of the inputs.

To create a larger multiplexer, you combine two smaller multiplexers together. For example, Fig. 12.34 shows two 8-line-to-1-line 74HC151s combined to create a 16-line-to-1-line multiplexer. Another alternative is to use a 16-line-to-1-line multiplexer IC like the 74HC150 shown in the figure. Check the catalogs to see what other kinds of multiplexers are available.


FIGURE 12.34

Finally, let’s take a look at a very useful device called a bilateral switch. An example bilateral switch IC is the 4066, shown to the far right in Fig. 12.32. Unlike the multiplexer, this device merely acts as a digitally controlled quad SPST switch or quad transmission gate. Using a digital control input, you select which switches are on and which switches are off. To turn on a given switch, apply a high level to the corresponding switch select input; otherwise, keep the select input low.

In Sec. 12.9, we will look at analog switches and multiplexers. These devices use digital select inputs to control analog signals. Analog switches and multiplexers become important when you start linking the digital world to the analog world.

12.3.2 Demultiplexers (Data Distributors) and Decoders

A demultiplexer (or data distributor) is the opposite of a multiplexer. It takes a single data input and routes it to one of several possible outputs. A simple four-line demultiplexer built from logic gates is shown on the left side of Fig. 12.35. To select the output (A, B, C, or D) to which you want to send the input signal (applied at E), you apply logic levels to the data select inputs (S0, S1), as shown in the truth table.


FIGURE 12.35

Notice that the unselected outputs assume a high level, while the selected output varies with the input signal. An IC that contains two functionally separate four-line demultiplexers is the 74HC139, shown on the right side of Fig. 12.35. If you need more outputs, check out the 75xx154 16-line demultiplexer. This IC uses four data select inputs to choose from 1 of 16 possible outputs. Check out the catalogs to see what other demultiplexers exist.

A decoder is somewhat like a demultiplexer, but it does not route input data to a specific output via data select inputs. Instead, it simply uses the data select inputs to choose which output (or outputs) among many are to be made high or low. The number of address inputs, the number of outputs, and the active state of the selected output vary from decoder to decoder. The variance is based on what the decoder is designed to do. For example, the 74LS138 1-of-8 decoder shown in Fig. 12.36 uses a 3-bit address input to select which of eight outputs will be made low; all other outputs are held high. Like the demultiplexer in Fig. 12.35, this decoder has active-low outputs.


FIGURE 12.36

Now what exactly does it mean to say an output is an active-low output? It simply means that when an active-low output is selected, it is forced to a low logic state; otherwise, it is held high. Active-high outputs behave in the opposite manner. An active-low output is usually indicated with a bubble, although sometimes it is indicated with a barred variable within the IC logic symbol—no bubble included. Active-high outputs have no bubbles. Both active-low and active-high outputs are equally common among ICs.

By placing a load (for example, a warning LED) between +VCC and an active-low output, you can sink current through the load and into the active-low output when the output is selected. By placing a load between an active-high output and ground, you can source current from the active-high output and sink it through the load when the output is selected. The limits to how much current an IC can source or sink will be discussed in Sec. 12.4, and various schemes used to drive analog loads will be presented in Sec. 12.9.

Now let’s get back to the 74LS138 decoder and discuss the remaining enable inputs For the 74LS138 to “decode,” you must make the active-low inputs and low, while making the active-high input E2 high. If any other set of enable inputs is applied, the decoder is disabled, making all active-low outputs high regardless of the selected inputs.

Other common decoders include the 7442 BCD-to-DEC (decimal) decoder, the 74154 1-of-16 (hex) decoder, and the 7447 BCD-to-seven-segment decoder shown in Figure 12.37. Like the preceding decoder, these devices also have active-low outputs. The 7442 uses a binary-coded decimal input to select 1 of 10 (0 through 9) possible outputs. The 74154 uses a 4-bit binary input to address 1 of 16 (0 through 15) outputs, making that output low (all others high), provided the enables are both set low.


FIGURE 12.37

Now the 7447 is a bit different from the other decoders. With this device, more than one output can be driven low at a time. This is important because it allows the 7447 to drive a seven-segment LED display; to create different numbers requires driving more than one LED segment at a time. For example, in Fig. 12.38, when the BCD number for 5 (0101) is applied to the 7447’s inputs, all outputs except and go low. This causes LED segments a, c, d, f, and g to light up—the 7447 sinks current through these LED segments, as indicated by the internal wiring of the display and the truth table.


FIGURE 12.38

The 7447 also comes with a lamp test active-low input that can be used to drive all LED segments at once to see if any of the segments are faulty. The ripple blanking input and ripple blanking output can be used in multistage display applications to suppress a leading-edge and/or trailing-edge zero in a multidigit decimal. For example, using the ripple blanking inputs and outputs, it is possible to take an eight-digit expression like 0056.020 and display 56.02, suppressing the two leading zeros and the one trailing zero. Leading-edge zero suppression is obtained by connecting the ripple blanking output of a decoder to the ripple blanking input of the next lower-stage device. The most significant decoder stage should have its ripple blanking input grounded. A similar procedure is used to provide automatic suppression of trailing zeros in the fractional part of the decimal.

12.3.3 Encoders and Code Converters

Encoders are the opposite of decoders. They are used to generate a coded output from a single active numeric input. To illustrate this in a simple manner, let’s take a look at the simple decimal-to-BCD encoder circuit shown in Fig. 12.39.


FIGURE 12.39

In this circuit, normally all lines are held high by the pullup resistors connected to +5 V. To generate a BCD output that is equivalent to a single selected decimal input, the switch corresponding to that decimal is closed. (The switch acts as an active-low input.) The truth table in Fig. 12.39 explains the rest.

Figure 12.40 shows a 74LS147 decimal-to-BCD (ten-line-to-four-line) priority encoder IC. The 74LS147 provides the same basic function as the circuit shown in Fig. 12.39, but it has active-low outputs. This means that instead of getting an LLHH output when 3 is selected, as in the previous encoder, you get HHLL. The two outputs represent the same thing (3); one is expressed in positive true logic, and the other (the 74LS147) is expressed in negative true logic. If you do not like negative true logic, you can slap inverters on the outputs of the 74LS147 to get positive true logic. The choice to use positive or negative true logic really depends on what you are planning to drive. For example, negative true logic is useful when the device that you wish to drive uses active-low inputs.


FIGURE 12.40

Another important difference between the two encoders is the priority that is used with the 74LS147 and not used with the encoder in Fig. 12.39. The term priority is applied to the 74LS147 because this encoder is designed so that if two or more inputs are selected at the same time, it will select only the larger-order digit. For example, if 3, 5, and 8 are selected at the same time, only the 8 (negative true BCD LHHH or 0111) will be output. The truth table in Fig. 12.40 demonstrates this; look at the “don’t care” or “X” entries. With the nonpriority encoder, if two or more inputs are applied at the same time, the output will be unpredictable.

The circuit shown in Fig. 12.41 provides a simple illustration of how an encoder and a decoder can be used together to drive an LED display via a 0 through 9 keypad. The 74LS147 encodes a keypad’s input into BCD (negative logic). A set of inverters then converts the negative true BCD into positive true BCD. The transformed BCD is then fed into a 7447 seven-segment LED display decoder/driver IC.


FIGURE 12.41

Figure 12.42 shows a 74148 octal-to-binary priory encoder IC. It is used to transform a specified single octal input into a binary 3-bit output code. As with the 74LS147, the 74148 comes with a priority feature, so if two or more inputs are selected at the same time, only the higher-order number is selected.


FIGURE 12.42

A high applied to the input enable forces all outputs to their inactive (high) state and allows new data to settle without producing erroneous information at the outputs. A group signal output and an enable output are also provided to allow for system expansion. The output is active level low when any input is low (active). The output is low (active) when all inputs are high. Using the output enable along with the input enable allows priority coding of N input signals. Both and are active high when the input enable is high (device disabled).

Figure 12.43 shows a 74184 BCD-to-binary converter (encoder) IC. This device has eight active-high outputs (Y1Y8). Outputs Y1 to Y5 are outputs for regular BCD-to-binary conversion, while outputs Y6 to Y8 are used for a special BDC code called nine’s complement and ten’s complement. The active-high BCD code is applied to inputs A through E. The input is an active-low enable input.


FIGURE 12.43

A sample 6-bit BCD-to-binary converter and a sample 8-bit BCD-to-binary converter that use the 74184 are shown to the right in Fig. 12.43. In the 6-bit circuit, since the LSB of the BCD input is always equal to the LSB of the binary output, the connection is made straight from input to output. The other BCD bits are applied directly to inputs A through E. The binary weighing factors for each input are A = 2, B = 4, C = 8, D = 10, and E = 20. Because only 2 bits are available for the MSD BCD input, the largest BCD digit in that position is 3 (binary 11). To get a complete 8-bit BCD converter, you connect two 74184s together, as shown to the far right in Fig. 12.43.

Figure 12.44 shows a 74185 binary-to-BCD converter (encoder). It is essentially the same as the 74184, but in reverse. The figure shows 6-bit and 8-bit binary-to-BCD converter arrangements.


FIGURE 12.44

12.3.4 Binary Adders

If you find yourself needing to do arithmetic in logic, then that is a pretty sure sign that you need to use a microcontroller. However, that microcontroller will contain exactly the sort of logic that we describe here in its arithmetic logic unit (ALU), so it is instructive to see how it works under the hood.

With a few logic gates, you can create a circuit that adds binary numbers. The mechanics of adding binary numbers is basically the same as that of adding decimal numbers. When the first digit of a two-digit number is added, a 1 is carried and added to the next row whenever the count exceeds binary 2 (for example., 1 + 1 = 10, or = 0 carry a 1). For numbers with more digits, you have multiple carry bits.

To demonstrate how you can use logic gates to perform basic addition, start out by considering the half-adder circuits in Fig. 12.45. Both half-adders shown are equivalent; one simply uses XOR/AND logic, while the other uses NOR/AND logic. The half-adder adds two single-bit numbers A and B and produces a 2-bit number. The LSB is represented as Σ0, and the MSB, or carry bit, is represented as Cout.


FIGURE 12.45

The most complicated operation the half-adder can do is 1 + 1. To perform addition on a two-digit number, you must attach a full-adder circuit (shown in Fig. 12.45) to the output of the half-adder. The full-adder has three inputs: two to input the second digits of the two binary numbers (A1, B1), and another that accepts the carry bit from the half-adder (the circuit that added the first digits, A0 and B0, of the two numbers). The two outputs of the full-adder will provide the 2d-place digit sum Σ1 and another carry bit that acts as the third-place digit of the final sum. Now, you can keep adding more full-adders to the half-adder/full-adder combination to add larger numbers, linking the carry bit output of the first full-adder to the next full-adder, and so forth. To illustrate this point, a 4-bit adder is shown in Fig. 12.45.

A number of 4-bit full-adder ICs are available, such as the 74LS283 and 4008. These devices will add two 4-bit binary numbers and provide an additional input carry bit, as well as an output carry bit, so you can stack them together to get adders that are 8-bit, 12-bit, 16-bit, and so on. For example, Fig. 12.46 shows an 8-bit adder made by cascading two 74LS283 4-bit adders.


FIGURE 12.46

12.3.5 Binary Adder/Subtractor

Figure 12.47 shows how two 74LS283 4-bit adders can be combined with an XOR array to yield an 8-bit 2’s complement adder/subtractor. The first number X is applied to the X0 through X7 inputs, while the second number Y is applied to the Y0 through Y7 inputs.


FIGURE 12.47

To add X and Y, the add/subtract switch is thrown to the add position, making one input of all XOR gates low. This has the effect of making the XOR gates appear transparent, allowing Y values to pass to the 74LS283s’ B inputs (X values are passed to the A inputs). The 8-bit adder then adds the numbers and presents the result to the Σ outputs.

To subtract Y from X, you must first convert Y into 1’s complement form; then you must add 1 to get Y into 2’s complement form. After that you simply add X to the 2’s complemented form of Y to get XY. When the add/subtract switch is thrown to the subtract position, one input to each XOR gate is set high. This causes the Y bits that are applied to the other XOR inputs to become inverted at the XOR outputs—you have just taken the 1’s complement of Y. The 1’s complement bits of Y are then presented to the inputs of the 8-bit adder. At the same time, Cin of the left 74LS283 is set high via the wire (see Fig. 12.47) so that a 1 is added to the 1’s complement number to yield a 2’s complement number. The 8-bit adder then adds X and the 2’s complement of Y together. The final result is presented at the Σ outputs. In the figure, 76 is subtracted from 28.

12.3.6 Comparators and Magnitude Comparator ICs

A digital comparator is a circuit that accepts two binary numbers and determines whether the two numbers are equal. For example, Fig. 12.48 shows a 1-bit and a 4-bit comparator. The 1-bit comparator outputs a high (1) only when the two 1-bit numbers A and B are equal. If A is not equal to B, then the output goes low (0). The 4-bit is basically four 1-bit comparators in one. When all individual digits of each number are equal, all XOR gates output a high, which in turn enables the AND gate, making the output high. If any two corresponding digits of the two numbers are not equal, the output goes low.


FIGURE 12.48

Now, say you want to know which number, A or B, is larger. The circuits in Fig. 12.48 will not do the trick. What you need instead is a magnitude comparator like the 74HC85 shown in Fig. 12.49. This device not only tells you if two numbers are equal, but also which number is larger. For example, if you apply a 1001 (910) to the A3A2A1A0 inputs and a second number 1100 (1210) to the B3B2B1B0 inputs, the A < B output will go high (the other two outputs, A > B and A = B, will remain low). If A and B were equal, the A = B output would have gone high, and so on. If you wanted to compare larger numbers—say, two 8-bit numbers—you simply cascade two 74HC85 comparators together, as shown on the right side of Fig. 12.49. The leftmost 74HC85 compares the lower-order bits, while the rightmost 74HC85 compares the higher-order bits. To link the two devices together, you connect the output of the lower-order device to the expansion inputs of the higher-order device, as shown. The lower-order device’s expansion inputs are always set low (IA < B), high (IA = B), and low (IA > B).


FIGURE 12.49

12.3.7 A Note on Obsolescence and the Trend Toward Microcontroller Control

We have just covered most of the combinational devices you will find discussed in textbooks and listed within electronic catalogs. Many of these devices are still used. However, some devices, such as the binary adders and code converters, are obsolete.

Today, the trend is to use software-controlled devices such as microcontrollers and FPGAs to carry out arithmetic operations and code conversions. Before you attempt to design any logic circuit, we suggest reading Chaps. 12 and 13 first.

Microcontrollers can be used to collect data, store data, and perform logical operations using the input data. They also can generate output signals that can be used to control displays, audio devices, stepper motors, servos, and so on. The specific functions a microcontroller is designed to perform depend on the program you store in its internal ROM-type memory.

Programming the microcontroller typically involves simply using a special programming unit provided by the manufacturer. The programming unit usually consists of a prototyping platform that is linked to a host computer (via a USB port) that is running a development environment. In the development environment, you typically write out a program in a high-level language such as C, or some other specialized language designed for a certain microcontroller, and then, with the press of a key, the program is converted into machine language (1s and 0s) and downloaded into the microcontroller’s memory.

In many applications, a single microcontroller can replace entire logic circuits composed of numerous discrete components.

Replacing logic circuits with a microcontroller is almost certainly going to be very cost-effective as small microcontrollers often cost less than a dollar. However, replacing physical logic with a program does have performance differences. It certainly won’t be as fast.

For systems where performance is important, FPGAs are probably a better approach. These are configured using either a logic gate schematic or a special purpose hardware description logic, and provide the flexibility of a microcontroller without sacrificing the raw speed of an implementation in logic gate ICs.

12.4 Logic Families

These days, pretty much all logic gates use CMOS technology.

In general, ICs made from MOSFET transistors use less space due to their simpler construction, have very high noise immunity, and consume less power than equivalent bipolar transistor ICs. Historically, the high-input impedance and input capacitance of the MOSFET transistors (due to their insulated gate leads) result in longer time constants for transistor on/off switching speeds when compared with bipolar gates, and therefore typically result in a slower device. Over years of development, however, the CMOS technology has overtaken other technologies.

Both the bipolar and MOSFET logic families can be divided into a number of subclasses and from a historical perspective, it is useful to see where we have come from and some of the more exotic technologies that exist. The major subclasses of the bipolar family include transistor-transistor logic (TTL), emitter-coupled logic (ECL), and integrated-injection logic (IIL or I2L). The major subclasses of the MOSFET logic include P-channel MOSFET (PMOS), N-channel MOSFET (NMOS), and complementary MOSFET (CMOS). CMOS uses both NMOS and PMOS technologies. The two most popular technologies are TTL and CMOS. The other technologies are typically used in large-scale integration devices, such as microprocessors and memories. There are new technologies popping up all the time, which yield faster, more energy-efficient devices. Some examples include BiCMOS, GaAS, SOS, and Josephson junction technologies.


FIGURE 12.50

As you have already learned, digital logic ICs are grouped into functional categories that get placed into either the 74HC00 or 4000 or 4000 CMOS series (or the improved 4000B series).

12.4.1 CMOS Family of ICs

While the 7400 series was going through its various transformations toward CMOS technology, the CMOS series entered the picture. The original CMOS 4000 series (or the improved 4000B series) was developed to offer lower power consumption than the TTL series of devices—a feature made possible by the high input impedance characteristics of its MOSFET transistors. The 4000B series also offered a larger supply voltage range (3 to 18 V), with minimum logic high = ⅔VDD and maximum logic low = ⅓VDD. The 4000B series, though more energy efficient than the TTL series, was significantly slower and more susceptible to damage due to electrostatic discharge. Figure 12.51 shows the internal circuitry of CMOS NAND, AND, and NOR gates. To figure out how the gates work, apply high (logic 1) or low (logic 0) levels to the inputs and see which transistor gates turn on and which transistor gates turn off.


FIGURE 12.51

A further improvement in speed over the original 4000B series came with the introduction of the 40H00 series. Although this series was faster than the 4000B series, it was not quite as fast as the 74LS TTL series. The 74C CMOS series also emerged on the scene, which was designed specifically to be pin-compatible with the TTL line.

Another significant improvement in the CMOS family came with the development of the 74HC and the 74HCT series. Both these series, like the 74C series, were pin-compatible with the TTL 74 series. The 74HC (high-speed CMOS) series had the same speed as the 74LS, as well as the traditional CMOS low-power consumption. The 74HCT (high-speed CMOS TTL compatible) series was developed to be interchangeable with TTL devices (same I/O voltage level characteristics). The 74HC series is very popular today.

Still further improvements in 74HC/74HCT series led to the advanced CMOS logic (74AC/74ACT) series. The 74AC (advanced CMOS) series approached speeds comparable with the 74F TTL series, while the 74ACT (advanced CMOS TTL compatible) series was designed to be TTL compatible.

12.4.2 I/O Voltages and Noise Margins

The exact input voltage levels required for a logic IC to perceive a high (logic 1) or low (logic 0) input level differ between the various logic families. At the same time, the high and low output levels provided by a logic IC vary among the logic families. For example, Fig. 12.52 shows valid input and output voltage levels for the 74HC (CMOS) families.

In Fig. 12.52, the voltage ranges are represented as follows:

· VIH represents the valid voltage range that will be interpreted as a high logic input level.

· VIL represents the valid voltage range that will be interpreted as a low logic input level.

· VOL represents the valid voltage range that will be guaranteed as a low logic output level.

· VOH represents the valid voltage range that will be guaranteed as a high logic output level.


FIGURE 12.52

12.4.3 Current Ratings, Fanout, and Propagation Delays

Logic IC inputs and outputs can sink or source only a given amount of current. IIL is defined as the maximum low-level input current, IIH as the maximum high-level input current, IOH as the maximum high-level output current, and IOL as the maximum low-level output current.

The limit to how much current a device can sink or source determines the size of loads that can be attached. The term fanout is used to specify the total number of gates that can be driven by a single gate of the same family without exceeding the current rating of the gate. The fanout is determined by taking the smaller result of IOL/IIL or IOH/IIH. For the 7HC, it is around 50.

12.5 Powering and Testing Logic ICs

Most logic devices will work with 5 V supplies like the ones shown in Fig. 12.53.


FIGURE 12.53

12.5.1 Power Supply Decoupling

When a logic device makes a low-to-high or a high-to-low level transition, there is an interval during which the conduction times in the upper and lower totem-pole output transistors overlap. During this interval, a drastic change in power supply current occurs, which results in a sharp, high-frequency current spike within the supply line. If a number of other devices are linked to the same supply, the unwanted spike can cause false triggering of these devices. The spike also can generate unwanted electromagnetic radiation.

To avoid unwanted spikes within logic systems, decoupling capacitors can be used. A decoupling capacitor, typically multilayer ceramic, from 0.01 to 0.1 µF (>5 V), is placed directly across the VCC-to-ground pins of each IC in the system. The capacitors absorb the spikes and keep the VCC level at each IC constant, thus reducing the likelihood of false triggering and generally electromagnetic radiation. Decoupling capacitors should be placed as close to the ICs as possible to keep current spikes local, instead of allowing them to propagate back toward the power supply. You can usually get by with using one decoupling capacitor for every five to ten gates or one for every five counter or register ICs.

12.5.2 Unused Inputs

Unused inputs that affect the logical state of a chip should not be allowed to float. Instead, they should be tied high or low, as necessary (floating inputs are liable to pick up external electrical noise, which leads to erratic output behavior). For example, a four-input NAND gate that uses only two inputs should have its two unused inputs held high to maintain proper logic operation. A three-input NOR gate that uses only two inputs should have its unused input held low to maintain proper logic operation. Likewise, the CLEAR and PRESET inputs of a flip-flop should be grounded or tied high, as appropriate.

If there are unused sections within an IC (for example, unused logic gates within a multigate package), the inputs that link to these sections may pick up unwanted charge and may reach a voltage level that causes output MOS transistors to conduct simultaneously, resulting in a large internal current spike from the supply (VDD) to ground. The result can lead to excessive supply current drain and IC damage. To avoid this fate, inputs of unused sections of a CMOS IC should be grounded. Figure 12.54 illustrates what to do with unused inputs for NAND and NOR ICs.


FIGURE 12.54

As a last note of caution, never drive CMOS inputs when the IC’s supply voltage is removed. Doing so can damage the IC’s input protection diodes.

12.5.3 Logic Probes and Logic Pulsers

Two simple tools used to test logic ICs and circuits include the test probe and logic pulser, as shown in Fig. 12.55.


FIGURE 12.55

A typical logic probe comes in a pen-like package, with metal probe tip and power supply wires: one red and one black. Red is connected to the positive supply voltage of the digital circuit (VCC), and black is connected to the ground (VSS) of the circuit. To test a logic state within a circuit, the metal tip of the probe is applied. If a high voltage is detected, the probe’s high LED lights up; if a low voltage is detected, the probe’s low LED turns off.

Along with performing simple static tests, logic probes can perform a few simple dynamic tests, such as detecting a single momentary pulse that is too fast for the human eye to detect or detecting a pulse train, such as a clock signal. To detect a single pulse, the probe’s PULSE/MEMORY switch is thrown to the MEMORY position. When a single pulse is detected, the internal memory circuit remembers the single pulse and lights up both the HI LED and PULSE LED at the same time. To clear the memory to detect a new single pulse, the PULSE/MEMORY switch is toggled. To detect a pulse train, the PULSE/MEMORY switch is thrown to the PULSE position. When a pulse train is detected, the PULSE LED flashes on and off.

Logic probes usually will detect single pulses with widths as narrow as 10 ns and will detect pulse trains with frequencies around 100 MHz. Check the specifications that come with your probe to determine these minimum and maximum limits.

A logic pulser allows you to send a single logic pulse or a pulse train through an IC and circuits, where the results of the applied pulses can be monitored by a logic probe. Like a logic probe, the pulser comes with similar supply leads. To send a single pulse, the SINGLE-PULSE/PULSE-TRAIN switch is set to SINGLE-PULSE, and then the SINGLE-PULSE button is pressed. To send a pulse train, switch to PULSE-TRAIN mode. With the pulser model shown in Fig. 12.55, you get to select either 1 pulse per second (pps) or 500 pps.

12.6 Sequential Logic

The combinational circuits covered previously (encoders, decoders, multiplexers, parity generators/checkers, and so on) have the property of input-to-output immediacy. This means that when input data is applied to a combinational circuit, the output responds almost immediately. Now, combinational circuits lack a very important characteristic: they cannot store information. A digital device that cannot store information is not very interesting, practically speaking.

To provide “memory” to circuits, you must create devices that can latch onto data at a desired moment in time. The realm of digital electronics devoted to this subject is referred to as sequential logic. This branch of electronics is referred to as sequential because for data bits to be stored and retrieved, a series of steps must occur in a particular order. For example, a typical set of steps might involve first sending an enable pulse to a storage device, and then loading a group of data bits all at once (parallel load), or perhaps loading a group of data bits in a serial manner, which takes a number of individual steps. At a later time, the data bits may need to be retrieved by first applying a control pulse to the storage device. A series of other pulses might be required to force the bits out of the storage device.

To push bits through sequential circuits usually requires a clock generator. The clock generator is similar to the human heart. It generates a series of high and low voltages (analogous to a series of high and low pressures as the heart pumps blood) that can set bits into action. The clock also acts as a time base on which all sequential actions can be referenced. Clock generators will be discussed in detail in Sec. 12.6.7. Now, let’s take a look at the most elementary of sequential devices: the SR flip-flop.

12.6.1 SR Flip-Flops

The most elementary data-storage circuit is the set-reset (SR) flip-flop, also referred to as a transparent latch. There are two basic kinds of SR flip-flops: the cross-NOR SR flip-flop and the cross-NAND SR flip-flop.

Consider the cross-NOR SR flip-flop shown in Fig. 12.56. At first, it appears that figuring out what the cross-NOR SR flip-flop does given only two input voltages is impossible, since the NOR gates’ inputs depend on the outputs, and what are the outputs anyway? (For now, pretend that Q and are not complements but separate variables; you could call them X and Y if you like.) Well, first of all, you know that a NOR gate will output a high (logic 1) only if both inputs are low (logic 0). From this, you can deduce that if S = 1 and R = 0, Q must be 1 and must be 0, regardless of the outputs. This is called the set condition. Likewise, by similar argument, we can deduce that if S = 0 and R = 1, Q must be 0 and must be 1. This is called the reset condition.


FIGURE 12.56

But now, what about R = 0 and S = 0? Can you predict the outputs given only input levels? No! It is impossible to predict the outputs because the outputs are essential for predicting the outputs—it is a “catch-22.” However, if you know the states of the outputs beforehand, you can figure things out. For example, if you first set the flip-flop (S = 1, R = 0, Q = 1, = 0), and then apply S = 0, R = 0, the flip-flop would remain set (upper gate: S = 0, Q = 1 → = 0; lower gate: R = 0, = 0 → Q = 1). Likewise, if you start out in reset mode (S = 0, R = 1, Q = 0, = 0), and then apply S = 0, R = 0, the flip-flop remains in reset mode (upper gate: S = 0, Q = 0 → = 1; lower gate: R = 0, =1 → Q = 0). In other words, the flip-flop remembers, or latches onto, the previous output state even when both inputs go low (0). This is referred to as the hold condition.

The last choice you have is S = 1, R = 1. Here, it is easy to predict what will happen because you know that as long as there is at least one high (1) applied to the input to the NOR gate, the output will always be 0. Therefore, Q = 0 and = 0. Now, there are two fundamental problems with the S = 1, R = 1 state. First, why would you want to set and reset at the same time? Second, when you return to the hold condition from S = 1, R = 1, you get an unpredictable result, unless you know which input returned low last. Why? When the inputs are brought back to the hold position (R = 0, S = 0, Q = 0, = 0), both NOR gates will want to be 1 (they want to be held). But let’s say one of the NOR gate’s outputs changes to 1 a fraction of a second before the other. In this case, the slower flip-flop will not output a 1 as planned, but will instead output 0. This is a classic example of a race condition, where the slower gate loses. But which flip-flop is the slower one? This unstable, unpredictable state cannot be avoided and is simply not used.

The cross-NAND SR flip-flop provides the same basic function as the NOR SR flip-flop, but there is a fundamental difference: its hold and indeterminate states are reversed. This occurs because, unlike the NOR gate, which outputs a high only when both its inputs are low, the NAND gate outputs a low only when both its inputs high. This means that the hold condition for the cross-NAND SR flip-flop is = 1, = 1, while the indeterminate condition is = 0, = 0.

Now let’s look at two simple applications for SR flip-flops.

Switch Debouncer

Say you want to use the far-left switch/pullup resistor circuit (see Fig. 12.57) to drive an AND gate’s input high or low (the other input is fixed high). When the switch is open, the AND gate should receive a high. When the switch is closed, the gate should receive a low. That’s what should happen, but that’s not what actually happens. Why? Because of switch bounce.


FIGURE 12.57

When a switch is closed, the metal contacts bounce a number of times before coming to rest due to inherent springlike characteristics of the contacts. Though the bouncing typically lasts no more than 50 ms, the results can lead to unwanted false triggering, as shown in the far left circuit in Fig. 12.57.

A simple way to get rid of switch bounce is to use the switch debouncer circuit, shown at center of Fig. 12.57. This circuit uses an SR flip-flop to store the initial switch contact voltage while ignoring all trailing bounces. In this circuit, when the switch is thrown from the B to A position, the flip-flop is set. As the switch bounces alternately high and low, the Q output remains high, because when the switch contact bounces away from A, the S input receives a low (R is low, too), but that’s just a hold condition; the output stays the same. The same debouncing feature occurs when the switch is thrown from position A to B.

Latched Temperature or Light Alarm

The simple circuit in Fig. 12.57 uses an SR flip-flop to sound a buzzer alarm when the temperature (when using a thermistor) or the light intensity (when using a photoresistor) reaches a critical level. When the temperature or light increases, the resistance of the thermistor or photoresistor decreases, and the R input voltage goes down. When the R input voltage goes below the high threshold level of the NAND gate, the flip-flop is set, and the alarm is sounded. The alarm will continue to sound until the RESET switch is pressed and the temperature or light level has gone below the critical triggering level. The pot is used to adjust this level.

Level-Triggered SR Flip-Flop (the Beginning of Clocked Flip-Flops)

Now it would be nice to make an SR flip-flop synchronous; that is, make the S and R inputs either enabled or disabled by a control pulse, such as a clock. Only when the clock pulse arrives are the inputs sampled. Flip-flops that respond in this manner are referred to as synchronous or clocked flip-flops (as opposed to the preceding asynchronous flip-flops).

To make the preceding SR flip-flop into a synchronous or clocked device, simply attach enable gates to the inputs of the flip-flop, as shown in Fig. 12.58. The figure shows the cross-NAND arrangement, but a cross-NOR arrangement also can be used. In this setup, only when the clock is high are the S and R inputs enabled. When the clock is low, the inputs are disabled, and the flip-flop is placed in hold mode. The truth table and timing diagram in Fig. 12.58 help illustrate how this device works.


FIGURE 12.58

Edge-Triggered SR Flip-Flops

The level-triggered SR flip-flop has an annoying feature: its S and R inputs must be held at the desired input condition (set, reset, or no change) for the entire time that the clock signal is enabling the flip-flop. With a slight alteration, however, you can make the level-triggered flip-flop more flexible (in terms of timing control) by turning it into an edge-triggered flip-flop.

An edge-triggered flip-flop samples the inputs only during either a positive or negative clock edge (↑ = positive edge, ↓ = negative edge). Any changes that occur before or after the clock edge are ignored—the flip-flop will be placed in hold mode.

To make an edge-triggered flip-flop, introduce either a positive or a negative level-triggered clock pulse generator network into the previous level-triggered flip-flop, as shown in Fig. 12.59.


FIGURE 12.59

In a positive edge-triggered generator circuit, a NOT gate with a propagation delay is added. Since the clock signal is delayed through the inverter, the output of the AND gate will not provide a low (as would be the case without a propagation delay), but will provide a pulse that begins at the positive edge of the clock signal and lasts for a duration equal to the propagation delay of the NOT gate. It is this pulse that is used to clock the flip-flop.

Within the negative edge-triggered generator network, the clock signal is first inverted and then applied through the same NOT/AND network. The pulse begins at the negative edge of the clock and lasts for a duration equal to the propagation delay of the NOT gate. The propagation delay is typically so small (in nanoseconds) that the pulse is essentially an “edge.”

Pulse-Triggered SR Flip-Flops

A pulse-triggered SR flip-flop is a level-clocked flip-flop; however, for any change in output to occur, both the high and low levels of the clock must rise and fall. Pulse-triggered flip-flops are also called master-slave flip-flops; the master accepts the initial inputs and then “whips” the slave with its output when the negative clock edge arrives. Another analogy often used is to say that during the positive edge, the master gets cocked (like a gun), and during the negative clock edge, the slave gets triggered. Figure 12.60 shows a simplified pulse-triggered cross-NAND SR flip-flop.


FIGURE 12.60

The master is simply a clocked SR flip-flop that is enabled during the high clock pulse and outputs Y and (set, reset, or no change). The slave is similar to the master, but it is enabled only during the negative clock pulse (due to the inverter). The moment the slave is enabled, it uses the Y and outputs of the master as inputs, and then outputs the final result.

Notice the preset and clear inputs. These are called asynchronous inputs. Unlike the synchronous inputs, S and R, the asynchronous inputs disregard the clock and either clear (also called asynchronous reset) or preset (also called asynchronous set) the flip-flop. When − is high and is low, you get asynchronous reset, Q = 1, = 0, regardless of the CLK, S, and R inputs. These active-low inputs are therefore normally pulled high to make them inactive. The ability to apply asynchronous set and resets is often used to clear entire registers that consist of an array of flip-flops.

General Rules for Deciphering Flip-Flop Logic Symbols

Typically, you do not need to worry about constructing flip-flops from scratch. Instead, you buy flip-flop ICs, as discussed in the next section. Likewise, you do not need to worry about complex logic gate schematics. Instead, you use symbolic representations like the ones shown in Fig. 12.61. Although the symbols in the figure apply to SR flip-flops, the basic rules that are outlined can be applied to the D and JK flip-flops, which are discussed in the following sections.


FIGURE 12.61

12.6.2 SR Flip-Flop ICs

Occasionally, it can make sense to use a sequential logic IC rather than a microcontroller or FPGA, but gradually if you require more than one or two ICs, you should probably consider a microcontroller or FPGA. Figure 12.62 shows a few sample SR flip-flop (latch) ICs. Always remember that switch debouncing with hardware logic costs money to make, but software switch debouncing for a switch connected to a microcontroller is free. It’s just an extra line or two of program code. The 74LS279A contains four independent SR latches (note that two of the latches have an EXTRA SET INPUT). This IC is commonly used in switch debouncers.


FIGURE 12.62

The 4043 contains four three-state cross-coupled NOR SR latches. Each latch has individual set and reset inputs, as well as separate Q outputs. The three-state feature is an extra bonus, which allows you to effectively disconnect all Q outputs, making it appear that the outputs are open circuits (high impedance, or high Z). This three-state feature is often used in applications where a number of devices must share a common data bus. When the output data from one latch is applied to the bus, the outputs of other latches (or other devices) are disconnected via the high-Z condition. The 4044 is similar to the 4043 but contains four three-state cross-coupled NAND RS latches.

12.6.3 D-Type Flip-Flops

A D-type flip-flop (data flip-flop) is a single input device. It is basically an SR flip-flop, where S is replaced with D and R is replaced with (inverted D). The inverted input is tapped from the D input through an inverter to the R input, as shown in Fig. 12.63. The inverter ensures that the indeterminate condition (race, or not used state, S = 1, R = 1) never occurs. At the same time, the inverter eliminates the hold condition so that you are left with only set (D = 1) and reset (D = 0) conditions. The circuit in Fig. 12.63 represents a level-triggered D-type flip-flop.


FIGURE 12.63

To create a clocked D-type level-triggered flip-flop, first start with the clocked level-triggered SR flip-flop and throw in the inverter, as shown in Fig. 12.64.


FIGURE 12.64

To create a clocked, edge-triggered, D-type flip-flop, take a clocked edge-triggered SR flip-flop and add an inverter, as shown in Fig. 12.65.


FIGURE 12.65

Figure 12.66 shows a popular edge-triggered D-type flip-flop IC, the 7474 (for example, the 74HC74). It contains two D-type positive edge-triggered flip-flops with asynchronous preset and clear inputs.


FIGURE 12.66

Note the lowercase letters l and h in the truth table in this figure. The h is similar to the H for a high voltage level, and the l is similar to the L for low voltage level; however, there is an additional condition that must be met for the flip-flop’s output to do what the truth table indicates. The additional condition is that the D input must be fixed high (or low) in duration for at least one setup time (ts) before the positive clock edge. This condition stems from the real-life propagation delays present in flip-flop ICs. If you try to make the flip-flop switch states too fast (do not give it time to move electrons around), you can end up with inaccurate output readings. For the 7474, the setup time is 20 ns. Therefore, when using this IC, you must not apply input pulses that are within the 20-ns limit. Other flip-flops will have different setup times, so you will need to check the manufacturer’s data sheets. We will discuss setup time and some other flip-flop timing parameters in greater detail in Sec. 12.6.6.

D-type flip-flops are sometimes found in the pulse-triggered (master-slave) variety. Recall that a pulse-triggered flip-flop requires a complete clock pulse before the outputs will reflect what is applied at the input(s) (in this case, the D input). Figure 12.67 shows the basic structure of a pulse-triggered D flip-flop. It is almost exactly like the pulse-triggered SR flip-flop, except for the inverter addition to the master’s input.


FIGURE 12.67

Now let’s look at a few simple D-type flip-flop applications.

Stop and Go

In the stop-go indicator circuit, a simple level-triggered D-type flip-flop is used to turn on a red LED when its D input is low (reset) and turn on a green LED when the D input is high (set). Only one LED can be turned on at a time.

The divide-by-two counter uses a positive edge-triggered D-type flip-flop to divide an applied signal’s frequency by two. The explanation of how this works is simple: The positive edge-triggered feature does not care about negative edges. You can figure out the rest.

External Asynchronous Control Signal

A synchronizer is used when you want to use an external asynchronous control signal (perhaps generated by a switch or other input device) to control some action within a synchronous system. The synchronizer provides a means of keeping the phase of the action generated by the control signal in synch with the phase of the synchronous system.

For example, say you want an asynchronous control signal to control the number of clock pulses that get from point A to point B within a synchronous system. You might try using a simple enable gate, as shown below the synchronizer circuit in Fig. 12.68. However, because the external control signal is not synchronous (in phase) with the clock, when you apply the external control signal, you may shorten the first or last output pulse, as shown in the lower timing diagram.


FIGURE 12.68

Certain applications do not like shortened clock pulses and will not function properly. To avoid shortened pulses, throw in an edge-triggered D-type flip-flop to create a synchronizer. The flip-flop’s CLK input is tapped off the input clock line, its D input receives the external control signal, and its Q output is connected to the AND gate’s enable input. With this arrangement, there will never be shortened clock pulses because the Q output of the flip-flop will not supply enable pulses to the AND gate that are out of phase with the input clock signal. This is due to the fact that after the flip-flop’s CLK input receives a positive clock edge, the flip-flop ignores any input changes applied to the D input until the next positive clock edge.

12.6.4 Quad and Octal D Flip-Flops

Most frequently, you will find a number of D flip-flops or D latches grouped together within a single IC. For example, the 74HC75, shown in Fig. 12.69, contains four transparent D latches. Latches 0 and 1 share a common active-low enable E0E1, while latches 2 and 3 share a common active-low enable E2E3. From the function table, each Q output follows each D input as long as the corresponding enable line is high. When the enable line goes low, the Q output will become latched to the value that D was one setup time prior to the high-to-low enable transition. The 4042 is another quad D-type latch, which works as described in Fig. 12.69. D-type latches are commonly used as data registers in bus-oriented systems, as is also explained in the figure.


FIGURE 12.69

D flip-flops also come in octal form—eight flip-flops per IC. These devices are frequently used as 8-bit data registers within microprocessor systems, where devices share 8-bit or 2 × 8 = 16-bit data or address buses. An example of an octal D-type flip-flop is the 74HCT273 shown in Fig. 12.70. All D flip-flops within the 74HCT273 share a common positive edge-triggered clock input and a common active-low clear input. When the clock input receives a positive edge, data bits applied to D0 through D7 are stored in the eight flip-flops and appear at the outputs Q0 through Q7. To clear all flip-flops, the clear input is pulsed low.


FIGURE 12.70

12.6.5 JK Flip-Flops

Finally, we come to the last of the flip-flops: the JK flip-flop. A JK flip-flop resembles an SR flip-flop, where J acts like S and K acts like R. Likewise, it has a set mode (J = 1, K = 0), a reset mode (J = 0, K = 1), and a hold mode (J = 0, K = 0). However, unlike the SR flip-flop, which has an indeterminate mode when S = 1, R = 1, the JK flip-flop has a toggle mode when J = 1, K = 1. Toggle means that the Q and outputs switch to their opposite states at each active clock edge.

To make a JK flip-flop, modify the SR flip-flop’s internal logic circuit to include two cross-coupled feedback lines between the output and input. This modification, however, means that the JK flip-flop cannot be level-triggered; it can only be edge-triggered or pulse-triggered. Figure 12.71 shows how you can create edge-triggered flip-flops based on the cross-NAND SR edge-triggered flip-flop.


FIGURE 12.71

Edge-triggered JK flip-flops also come with preset (asynchronous set) and clear (asynchronous reset) inputs, as shown in Fig. 12.72.


FIGURE 12.72

There are pulse-triggered (master-slave) flip-flops, too. These devices are similar to the pulse-triggered SR flip-flops with the exception of the distinctive JK cross-coupled feedback connections from the slave’s Q and outputs back to the master’s input gates. Figure 12.73 shows a simple NAND pulse-triggered JK flip-flop.


FIGURE 12.73

The pulse-triggered flip-flops are not as popular as the edge-triggered JK flip-flops because of an undesired effect that can occur. Pulse-triggered JK flip-flops occasionally experience what is called ones-catching. In ones-catching, unwanted pulses or glitches caused by electrostatic noise appear on J and K while the clock is high. The flip-flop remembers these glitches and interprets them as true data. Ones-catching normally is not a problem when clock pulses are of short duration; it is when the pulses get long that you must watch out. To avoid ones-catching altogether, stick with edge-triggered JK flip-flops.

Two major applications for JK flip-flops are found within counter and shift register circuits. Here, we will introduce a counter application. We will discuss shift registers in Sec. 12.8 and additional counter circuits in Sec. 12.7.


FIGURE 12.74

Ripple Counter (Asynchronous Counter)

A simple counter, called a MOD-16 ripple counter (or asynchronous counter), can be constructed by joining four JK flop-flops together, as shown in Fig. 12.75. (MOD-16, or modulus 16, means that the counter has 16 binary states.) This means that it can count from 0 to 15—the 0 is one of the counts.


FIGURE 12.75

Each flip-flop in the ripple counter is fixed in toggle mode (J and K are both held high). The clock signal applied to the first flip-flop causes the flip-flop to divide the clock signal’s frequency by 2 at its Q0 output—a result of the toggle. The second flip-flop receives Q0’s output at its clock input and likewise divides by 2. The process continues down the line. What you get in the end is a binary counter with four digits. The LSB is Q0, while the MSB is Q3. When the count reaches 1111, the counter recycles back to 0000 and continues from there. To reset the counter at any given time, the active-low clear line is pulsed low. To make the counter count backward from 1111 to 0000, you would simply use the outputs.

The ripple counter in Fig. 12.75 also can be used as a divide-by-2, −4, −8, or −16 counter. Here, you simply replace the clock signal with any desired input signal that you wish to divide in frequency. To get a divide-by-2 counter, you only need the first flip-flop; to get a divide-by-8 counter, you need the first three flip-flops.

Ripple counters with higher MOD values can be constructed by slapping on more flip-flops to the MOD-16 counter. But how do you create a ripple counter with a MOD value other than 2, 4, 8, 16, and so on? For example, say you want to create a MOD-10 (0 to 9) ripple counter. And what do you do if you want to stop the counter after a particular count has been reached and then trigger some device, such as an LED or buzzer? Figure 12.76 shows just such a circuit.


FIGURE 12.76

To make a MOD-10 counter, you simply start with the MOD-16 counter and connect the Q0 and Q3 outputs to a NAND gate. When the counter reaches 9 (1001), Q0 and Q3 will both go high, causing the NAND gate’s output to go low. The NAND gate then sinks current, turning the LED on, while at the same time disabling the clock-enable gate and stopping the count. (When the NAND gate is high, there is no potential difference across the LED to light it up.) To start a new count, the active-low clear line is momentarily pulsed low. Now, to make a MOD-15 counter, you would apply the same basic approach used to the left, but you would connect Q1, Q2, and Q3 to a three-input NAND gate.

Synchronous Counter

There is a problem with the ripple counter just discussed. The output stages of the flip-flops further down the line (from the first clocked flip-flop) take time to respond to changes that occur due to the initial clock signal. This is a result of the internal propagation delay that occurs within a given flip-flop. A standard TTL flip-flop may have an internal propagation delay of 30 ns. If you join four flip-flops to create a MOD-16 counter, the accumulative propagation delay at the highest-order output will be 120 ns. When used in high-precision synchronous systems, such large delays can lead to timing problems.

To avoid large delays, you can create what is called a synchronous counter. Synchronous counters, unlike ripple (asynchronous) counters, contain flip-flops whose clock inputs are driven at the same time by a common clock line. This means that output transitions for each flip-flop will occur at the same time.

With this approach, unlike with the ripple counter, you must use some additional logic circuitry placed between various flip-flop inputs and outputs to give the desired count waveform. For example, to create a 4-bit MOD-16 synchronous counter requires adding two additional AND gates, as shown in Fig. 12.77. The AND gates act to keep a flip-flop in hold mode (if both inputs of the gate are low) or toggle mode (if both inputs of the gate are high), as follows:

· During the 0-1 count, the first flip-flop is in toggle mode (and always is); all the rest are in hold mode.

· When it is time for the 2-4 count, the first and second flip-flops are placed in toggle mode; the last two are held in hold mode.

· When it is time for the 4-8 count, the first AND gate is enabled, allowing the third flip-flop to toggle.

· When it is time for the 8-15 count, the second AND gate is enabled, allowing the last flip-flop to toggle.


FIGURE 12.77

You can work out the details for yourself by studying the circuit and timing waveforms.

The ripple (asynchronous) and synchronous counters discussed so far are simple but hardly ever used. In practice, if you need a counter—ripple or synchronous—you purchase a counter IC. These ICs are often MOD-16 or MOD-10 counters and usually come with many additional features. For example, many ICs allow you to preset the count to a desired number via parallel input lines. Others allow you to count up or to count down by means of control inputs. Counter ICs are discussed in Sec. 12.7.

12.6.6 Practical Timing Considerations with Flip-Flops

When working with flip-flops, it is important to avoid race conditions. For example, a typical race condition would occur if, say, you were to apply an active clock edge at the very moment you apply a high or low pulse to one of the inputs of a JK flip-flop. Since the JK flip-flop uses what is present on the inputs at the moment the clock edge arrives, having a high-to-low input change will cause problems because you cannot determine if the input is high or low at that moment—it is a straight line.

To avoid this type of race condition, you must hold the inputs of the flip-flop high or low for at least one setup time ts before the active clock transition. If the input changes during the ts to the clock edge region, the output levels will be unreliable.

To determine the setup time for a given flip-flop, you must look through the manufacturer’s data sheets. For example, the minimum setup time for the 74LS76 JK flip-flop is 20 ns. Other timing parameters, such as hold time and propagation delay, are also given by the manufacturers. A description of what these parameters mean is given in Fig. 12.78.

Flip-Flop Timing Parameters


FIGURE 12.78


Setup time ts: The time that the input must be held before the active clock edge for proper operation. For a typical flip-flop, ts is around 20 ns.

Hold time th: The time that the input must be held after the active clock edge for proper operation. For most flip-flops, this is 0 ns—meaning inputs need not be held beyond the active clock signal.

TPLH: Propagation delay from clock trigger point to the low-to-high Q output swing. A typical TPLH for a flip-flop is around 20 ns.

TPHL: Propagation delay from clock trigger point to the high-to-low Q output swing. A typical TPLH for a flip-flop is around 20 ns.

fmax: Maximum frequency allowed at the clock input. Any frequency above this limit will result in unreliable performance. This can vary greatly.

tW(L): Clock pulse width (low), the minimum width (in nanoseconds) that is allowed at the clock input during the low level for reliable operation.

tW(H): Clock pulse width (high), the minimum width (in nanoseconds) that is allowed at the clock input during the high level for reliable operation.

Preset or clear pulse width: Also given by tW(L), the minimum width (in nanoseconds) of the low pulse at the preset or clear inputs.

12.6.7 Digital Clock Generators and Single-Pulse Generators

You have already seen the importance of clock and single-pulse control signals. Now let’s take a look at some circuits that can generate these signals.

Clocks (Astable Multivibrators)

A clock is simply a squarewave oscillator. Chapter 10 discusses ways to generate squarewaves, so you can refer there to learn the theory. Here, we will simply present some practical circuits. Digital clocks can be constructed from discrete components such as logic gates, capacitors, resistors, and crystals, or can be purchased in IC form. Figure 12.79 shows some sample clock generators.


FIGURE 12.79

Figure a. Here, two CMOS inverters are connected together to form an RC relaxation oscillator with squarewave output. The output frequency is determined by the RC time constant, as shown in the figure.

Figure b. The previous oscillator has one problem: it may not oscillate if the transition regions of its two gates differ, or it may oscillate at a slightly lower frequency than the equation predicts due to the finite gain of the leftmost gate. The oscillator shown here resolves these problems by adding hysteresis via the additional RC network.

Figure c. This oscillator uses a pair of CMOS NAND gates and RC timing network along with a pot to set the frequency. A squarewave output is generated with a maximum frequency of around 2 MHz. The enable lead could be connected to the other input of the first gate, but here it is brought out to be used as a clock enable input (the clock is enabled when this lead is high).

Figure d. Here, a TTL SR flip-flop with dual feedback resistors uses an RC relaxation-type configuration to generate a squarewave. The frequency of the clock is determined by the R and C values, as shown in the figure. Changing the C1-to-C2 ratio changes the duty cycle.

Figure e. When high stability is required, a crystal oscillator is the best choice for a clock generator. Here, a pair of CMOS inverters and a feedback crystal are used (see Chap. 9 for details). The frequency of operation is determined by the crystal (such as 2 MHz or 10 MHz). Adjustment of the pot may be needed to start oscillations.

Figure f. A 555 timer in astable mode can be used to generate squarewaves. Here, we slap on a JK flip-flop that is in toggle mode to provide a means of keeping the low and high times the same, as well as providing clock-enable control. The timing diagram and the equations provided within the figure paint the rest of the picture.

Figure g. The 74S124 dual voltage-controlled oscillator (VCO) outputs squarewaves at a frequency that is dependent on the value of an external capacitor and the voltage levels applied its frequency-range input (VRNG) and its frequency control input (Vfreq). The graph in this figure shows how the frequency changes with capacitance, while VRNG and Vfreq are fixed at 2 V. This device also comes with active-low enable input. Other VCOs that are designed for clock generation include the 74LS624, 4024, and 4046 PLL (Phase Locked Loop). You will find many more listed in the catalogs.

Monostables (One-Shots)

To generate single-pulse signals of a desired width, you can use a discrete device called a monostable multivibrator, or one-shot for short. A one-shot has only one stable state, high (or low), and can be triggered into its unstable state, low (or high), for a duration of time set by an RC network. One-shots can be constructed from simple gates, capacitors, and resistors. These circuits, however, tend to be “finicky” and simply are not worth talking about. If you want a one-shot, you can buy a one-shot IC, which typically costs around 50 cents.

Two popular one-shots, shown in Fig. 12.80, are the 74121 nonretriggerable monostable multivibrator and the 74123 retriggerable monostable multivibrator.


The 74121 has three trigger inputs true and complemented outputs and timing inputs to which an RC network is attached (Rext/Cext, Cext). To trigger a pulse from the 74121, you can choose between five possible trigger combinations, as shown in the truth table in the figure. Bringing the input trigger in on B, however, is attractive when dealing with slowly rising or noisy signals, since the signal is directly applied to an internal Schmitt-triggered inverter (recall hystersis). To set the desired output pulse width (tw), a resistor/capacitor combination is connected to the Rext/Cext and Cext inputs, as shown. (An internal 2-k resistor is provided, which can be used alone by connecting pin 9 to VCC and placing the capacitor across pins 10 and 11, or which can be used in series with an external resistor attached to pin 9. Here, the internal resistor will not be used.) To determine which values to give to the external resistor and capacitor, use the formula given by the manufacturer, which is shown to the left. The maximum tw should not exceed 28 s (R = 40 k, C = 1000 µF) for reliable operation. Also, note that with a nonretriggerable one-shot like the 74121, any trigger pulses applied when the device is already in its astable state will be ignored.


The 74123 is a dual, retriggerable one-shot. Unlike nonretriggerable one-shots, this device will not ignore trigger pulses that are applied during the astable state. Instead, when a new trigger pulse arrives during an astable state, the astable state will continue to be astable for a time of tw. In other words, the device is simply retriggered. The 74123 has two trigger inputs and a clear input (CLR). When CLR is low, the one-shot is forced back into its stable state (Q = low). To determine tw, use the formula given to the left, provided Cext > 1000 pF. If Cext < 1000 pF, use tw/Cext/Rext graphs provided by the manufacturer to find tw.

FIGURE 12.80

Note that a 555 timer IC can also be used as a monostable and is a lower-cost device.

Besides acting as simple pulse generators, one-shots can be combined to make time-delay generators and timing and sequencing circuits (see Fig. 12.81).


FIGURE 12.81

If you do not have a one-shot IC like the 74121, you can use a 555 timer (discussed in Chap. 9) wired in its monostable configuration, as shown in Fig. 12.82.


FIGURE 12.82

One-Shot/Continuous-Clock Generator

The circuit shown in Fig. 12.83 is a handy one-shot/continuous clock generator that is useful when you start experimenting with logic circuits.


FIGURE 12.83

In this circuit, switch S2 is used to select whether a single-step or a continuous-clock input is to be presented to the output. When S2 is in the single-step position, the cross-NAND SR flip-flop (switch debouncer) is set (Q = 1, = 0). This disables NAND gate B while enabling NAND gate A, which will allow a single pulse from the one-shot to pass through gate C to the output. To trigger the one-shot, press switch S1. When S2 is thrown to the continuous position, the switch debouncer is reset (Q = 0, = 1). This disables NAND gate A and enables NAND gate B, allowing the clock signal generated by the 555/flip-flop to pass through gate C and to the output. (Just as a note to avoid confusion, you need gate C to prevent the output from being low and high at the same time.)

12.6.8 Automatic Power-Up Clear (Reset) Circuits

In sequential circuits, it is usually a good idea to clear (reset) devices when power is first applied. This ensures that devices, such as flip-flops and other sequential ICs, do not start out in a weird mode (for example, counter IC does not start counting at, say, 1101 instead of 0000). Figures 12.84 and 12.85 show some techniques used to provide automatic power-up clearing.


FIGURE 12.84


FIGURE 12.85

Let’s pretend that one of the devices in a circuit has a JK flip-flop that needs clearing during power-up. In order to clear the flip-flop and then quickly return it to synchronous operations, you would like to apply a low (0) voltage to its active-low clear input; afterward, you would like the voltage to go high (at least above 2.0 V for a 74LS76 JK flip-flop). A simple way to implement this function is to use an RC network like the one shown in the figure. When the power is off (switch open), the capacitor is uncharged (0 V). This means that the line is low (0 V). Once the power is turned on (switch closed), the capacitor begins charging up toward VCC (+5 V). However, until the capacitor’s voltage reaches 2.0 V, the line is considered low to the active-low clear input. After a duration of t = RC, the capacitor’s voltage will have reached 63 percent of VCC, or 3.15 V; after a duration of t = 5RC, its voltage will be nearly equal to +5 V. Since the 74LS76’s input requires at least 2.0 V to be placed back into synchronous operations, you know that t = RC is long enough. Thus, by rough estimate, if you want the line to remain low for 1 µs after power-up, you must set RC = 1 µs. Setting R = 1 k and C = 0.001 µF does the trick.

This automatic resetting scheme can be used within circuits that contain a number of resettable ICs. If an IC requires an active-high reset (not common), simply throw in an inverter and create an active-high clear line, as shown in the figure. Depending on the device being reset, the length of time that the clear line is at a low will be about 1 µs. As more devices are placed on the clear line, the low time duration will decrease due to the additional charging paths. To prevent this from occurring, a larger capacitor can be used.

An improved automatic power-up clear circuit is shown in Fig. 12.85. Here a Schmitt-triggered inverter is used to make the clear signal switch off cleanly. With CMOS Schmitt-triggered inverters, a diode and input resistor (R2) are necessary to protect the CMOS IC when power is removed.

12.6.9 Pullup and Pulldown Resistors

As you learned when dealing with the switch debouncer circuits, a pullup resistor is used to keep an input high that would otherwise float if left unconnected. If you want to set the “pulled up” input low, you can ground the pin, say, via a switch.

It is important to get an idea of the size of pullup resistor to use. The key here is to make the resistor value small enough so that the voltage drop across it does not weigh down the input voltage below the minimum high threshold voltage (VIH,min) of the IC. At the same time, you do not want to make it too small; otherwise, when you ground the pin, excessive current will be dissipated.

In the left diagram in Fig. 12.86, a 10-k pullup resistor is used to keep a 74LS device’s input high. To make the input low, close the switch. To figure out if the resistor is large enough so as not to weigh down the input, use Vin = +5 V − RIIH, where IIH is the current drawn into the IC during the high input state, when the switch is open. For a typical 74LS device, IIH is around 20 µA. Thus, by applying the simple formula, you find that Vin= 4.80 V, which is well above the VIH,min level for a 74LS device. Now, if you close the switch to force the input low, the power dissipated through the resistor (PD = V2/R) will be (5 V)2/10 k = 25 mW. The graph shown in Fig. 12.86 provides Vinversus R and PD versus R curves. As you can see, if R becomes too large, Vin drops below the VIH,min level, and the output will not go high as planned. As R gets smaller, the power dissipation skyrockets. To determine what value of R to use for a specific logic IC, you look up the VIH,min and IIH,max values within the data sheets and apply the simple formulas. In most applications, a 10-k pullup resistor will work fine.


FIGURE 12.86

You will run into situations where a pulldown resistor is used to keep a floating terminal low. Unlike a pullup resistor, the pulldown resistor must be smaller because the input low current IIL (sourced by IC) is usually much larger than IIH. Typically, a pulldown resistor is around 100 to 1 kΩ. A lower resistance ensures that Vin is low enough to be interpreted as a low by the logic input. To determine if Vin is low enough, use Vin = 0 V + IILR. As an example, use a 74LS device with an IIL = 400 µA and a 500-Ω pulldown resistor. When the switch is open, the input will be 0.20 V—well below the VIL,max level for the 74LS (∼0.8 V). When the switch is closed, the power dissipated by the resistor will be (5 V)2/500 Ω = 50 mW. The graph shown in Fig. 12.86 provides Vin versus R and PD versus R curves. As you can see by the curves, if R becomes too large, Vin surpasses VIL,max, and the output will not be low as planned. As R gets small, the power dissipation skyrockets. If you need to use a pulldown resistor/switch arrangement, be wary of the high power dissipation through the resistor when the switch is closed.

12.7 Counter ICs

In Sec. 12.6.5, you saw how flip-flops could be combined to make both asynchronous (ripple) and synchronous counters. In practice, using discrete flip-flops is to be avoided. Instead, use a prefabricated counter IC. These ICs cost a dollar or two and come with many additional features, like control enable inputs, parallel loading, and so on. A number of different kinds of counter ICs are available. They come in either synchronous (ripple) or asynchronous forms and are usually designed to count in binary or binary-coded decimal (BCD).

12.7.1 Asynchronous Counter (Ripple Counter) ICs

Asynchronous counters work fine for many noncritical applications, but for high-frequency applications that require precise timing, synchronous counters work better. Recall that unlike an asynchronous counter, a synchronous counter contains flip-flops that are clocked at the same time, and hence the synchronous counter does not accumulate nearly as many propagation delays as is the case with the asynchronous counter. Let’s look at a few asynchronous counter ICs you will find in the electronics catalogs.

7493 4-Bit Ripple Counter with Separate MOD-2 and MOD-8 Counter Sections

The 7493’s internal structure consists of four JK flip-flops connected to provide separate MOD-2 (0-to-1 counter) and MOD-8 (0-to-7 counter) sections. Both the MOD-2 and MOD-8 sections are clocked by separate clock inputs. The MOD-2 section uses Cp0 as its clock input, while the MOD-8 section uses Cp1 as its clock input. Likewise, the two sections have separate outputs: MOD-2’s output is Q0, while MOD-8’s outputs consist of Q1, Q2, and Q3. The MOD-2 section can be used as a divide-by-2 counter. The MOD-8 section can be used as a divide-by-2 counter (output tapped at Q1), a divide-by-4 counter (output tapped at Q2), or a divide-by-8 counter (output tapped at Q3). If you want to create a MOD-16 counter, simply join the MOD-2 and MOD-8 sections by wiring Q0 to Cp1, while using Cp0 as the single clock input.


FIGURE 12.87


FIGURE 12.88

The MOD-2, MOD-8, or the MOD-16 counter can be cleared by making both AND-gated master reset inputs (MR1 and MR2) high. To begin a count, one or both of the master reset inputs must be made low. When the negative edge of a clock pulse arrives, the count advances one step. After the maximum count is reached (1 for MOD-2, 111 for MOD-8, or 1111 for MOD-16), the outputs jump back to zero, and a new count begins.

7490 4-Bit Ripple Counter with MOD-2 and MOD-5 Counter Sections

The 7490, like the 7493, is another 4-bit ripple counter. However, its flip-flops are internally connected to provide MOD-2 (count-to-2) and MOD-5 (count-to-5) counter sections. Again, each section uses a separate clock: Cp0 for MOD-2 and Cp1 for MOD-5. By connecting Q0 to Cp1 and using Cp0 as the single clock input, a MOD-10 counter (decade or BCD counter) can be created.

When master reset inputs MR1 and MR2 are set high, the counter’s outputs are reset to 0—provided that master set inputs MS1 and MS2 are not both high (the MS inputs override the MR inputs). When MS1 and MS2 are high, the outputs are set to Q0 = 1, Q1 = 0, Q2 = 0, and Q3 = 1. In the MOD-10 configuration, this means that the counter is set to 9 (binary 1001). This master set feature comes in handy if you wish to start a count at 0000 after the first clock transition occurs (with master reset, the count starts out at 0001).

7492 Divide-by-12 Ripple Counter with MOD-2 and MOD-6 Counter Sections

The 7492 is another 4-bit ripple counter that is similar to the 7490. However, it has a MOD-2 and a MOD-6 section, with corresponding clock inputs Cp0 (MOD-2) and Cp1 (MOD-8). By joining Q0 to Cp1, you get a MOD-12 counter, where Cp0 acts as the single clock input. To clear the counter, high levels are applied to master reset inputs MR1 and MR2.


FIGURE 12.89

12.7.2 Synchronous Counter ICs

Like the asynchronous counter ICs, synchronous counter ICs come in various MOD arrangements. These devices usually come with extra goodies, such as controls for up or down counting and parallel load inputs used to preset the counter to a desired start count. Synchronous counter ICs are more popular than the asynchronous ICs, not only because of these additional features, but also because they do not have such long propagation delays as asynchronous counters. Let’s take a look at a few popular IC synchronous counters.

74193 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter

The 74193 is a versatile 4-bit synchronous counter that can count up or count down and can be preset to any count desired—at least a number between 0 and 15. There are two separate clock inputs: CpU is used to count up, and CpDis used to count down. One of these clock inputs must be held high in order for the other input to count. The binary output count is taken from Q0 (20), Q1 (21), Q2 (22), and Q3 (23).

To preset the counter to any desired count, a corresponding binary number is applied to the parallel inputs D0 to D3. When the parallel load input is pulsed low, the binary number is loaded into the counter, and the count, either up or down, will start from that number. The terminal count up ( ) and terminal count down ( ) outputs are normally high. The output is used to indicate when the maximum count has been reached and the counter is about to recycle to the minimum count (0000)—the carry condition. Specifically, this means that goes low when the count reaches 15 (1111) and the input clock (CpU) goes from high to low. remains low until CpU returns high. This low pulse at can be used as an input to the next high-order stage of a multistage counter. The terminal count down ( ) output is used to indicate that the minimum count has been reached (0000) and the counter is about to recycle to the maximum count 15 (1111)—the borrow condition. Specifically, this means that goes low when the down count reaches 0000 and the input clock (CpD) goes low. Figure 12.90 provides a truth table for the 74193, along with a sample load, up-count, and down-count sequence.


FIGURE 12.90

74192 Presettable Decade (BCD or MOD-10) Synchronous Up/Down Counter

The 74192, shown in Fig. 12.91, is essentially the same device as the 74193, except it counts up from 0 to 9 and repeats or counts down from 9 to 0 and repeats. When counting up, the terminal count up ( ) output goes low to indicate when the maximum count is reached (9 or 1001) and the CpU clock input goes from high to low. remains low until CpU returns high. When counting down, the terminal count down output ( ) goes low when the minimum count is reached (0 or 0000) and the input clock CpD goes low. The truth table and example load, count-up, and count-down sequence provided in Fig. 12.91 explain how the 74192 works in greater detail.


FIGURE 12.91

74190 Presettable Decade (BCD or MOD-10) and 74191 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counters

The 74190 and the 74191 do basically the same things as the 74192 and 74193, but the input and output pins, as well as the operating modes, are a bit different. (The 74190 and the 74191 have the same pinouts and operating modes; the only difference is the maximum count.) Like the previous synchronous counters, these counters can be preset to any count by using the parallel load operation. However, unlike the previous synchronous counters, to count up or down requires using a single input: . When is set low, the counter counts up; when is high, the counter counts down.

A clock enable input ( ) acts to enable or disable the counter. When is low, the counter is enabled. When is high, counting stops, and the current count is held fixed at the Q0 to Q3 outputs.

Unlike the previous synchronous counters, the 74190 and the 74191 use a single terminal count output (TC) to indicate when the maximum or minimum count has occurred and the counter is about to recycle. In count-down mode, TC is normally low but goes high when the counter reaches zero (for both the 74190 and 74191). In count-up mode, TC is normally low but goes high when the counter reaches 9 (for the 74190) or reaches 15 (for the 74191).

The ripple-clock output ( ) follows the input clock (CP) whenever TC is high. This means, for example, that in count-down mode, when the count reaches zero, will go low when CP goes low. The output can be used as a clock input to the next higher stage of a multistage counter. This, however, leads to a multistage counter that is not truly synchronous because of the small propagation delay from CP to of each counter. To make a multistage counter that is truly synchronous, you must tie each IC’s clock to a common clock input line. You use the TC output to inhibit each successive stage from counting until the previous stage is at its terminal count. Figure 12.92 shows various asynchronous (ripple-like) and synchronous multistage counters built from 74191 ICs.


FIGURE 12.92

Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter

The 74160 and 74163 resemble the 74190 and 74191 but require no external gates when used in multistage counter configurations. Instead, you simply cascade counter ICs together, as shown in Fig. 12.93.

For both devices, a count can be preset by applying the desired count to the D0 to D3 inputs and then applying a low to the parallel enable input ; the input number is loaded into the counter on the next low-to-high clock transition. The master reset is used to force all Q output low, regardless of the other input signals. The two clock enable inputs (CEP and CET) must be high for counting to begin. The terminal count output (TC) is forced high when the maximum count is reached, but will be forced low if CET goes low. This is an important feature that makes the multistage configuration synchronous, while avoiding the need for external gating. The truth tables along with the example load, count-up, and count-down timing sequences in Figs. 12.93 and 12.94 should help you better understand how these two devices work.


FIGURE 12.93


FIGURE 12.94

12.7.3 A Note on Counters with Displays

If you want to build a fairly sophisticated counter that can display many digits, the previous techniques are not worth pursuing, because there are simply too many discrete components to work with (for example, a separate seven-segment decoder/driver for each digit). A common alternative approach is to use a microcontroller or FPGA that functions both as a counter and a display driver.

What microcontrollers and FPGAs can do that discrete circuits have a hard time achieving is multiplex a display. In a multiplexed system, corresponding segments of each digit of a multidigit display are linked together, while the common lines for each digit are brought out separately. You can see that the number of lines is significantly reduced; a nonmultiplexed 7-segment 4-digit display has 28 segment lines and 4 common lines, while the 4-digit multiplexed display has only 7 + 4, or 11, lines.

The trick to multiplexing involves flashing each digit, one after the other (and recycling), in a fast enough manner to make it appear that the display is continuously lit. In order to multiplex, the microcontroller’s program must supply the correct data to the segment lines at the same time that it enables a given digit via a control signal sent to the common lead of that digit. We will talk about multiplexing displays in greater detail in Chap. 13 with microcontrollers and Chap. 14 using FPGAs.

60-Hz, 10-Hz, and 1-Hz Clock-Pulse Generator


FIGURE 12.95

This simple clock-pulse generator provides a unique way to generate 60-, 10-, and 1-Hz clock signals that can be used in applications that require real-time counting. The basic idea is to take the characteristic 60-Hz ac line voltage (from the wall socket) and convert it into a lower-voltage squarewave of the same frequency. (Note that countries other than the United States typically use 50 Hz instead of 60 Hz. For 50 Hz operation, use an appropriate transformer and replace the divide-by-6 counter with the divide-by-5 counter shown in the upper left of Fig. 12.94.) First, the ac line voltage is stepped down to 12.6 V by the transformer. The negative-going portion of the 12.6-V ac voltage is removed by the zener diode (which acts as a half-wave rectifier). At the same time, the zener diode clips the positive-going signal to a level equal to its reverse breakdown voltage (3.9 V). This prevents the Schmitt-triggered inverter from receiving an input level that exceeds its maximum input rating. The Schmitt-triggered inverter takes the rectified/chipped sine wave and converts it into a true squarewave. The Schmitt trigger’s output goes low (0.2 V) when the input voltage exceeds its positive threshold voltage VT+ (1.7 V) and goes high (3.4 V) when its input falls below its negative threshold voltage VT (0.9 V). From the inverter’s output, you get a 60-Hz squarewave (or a clock signal beating out 60 pulses per second). To get a 10-Hz clock signal, you slap on a divide-by-6 counter. To get a 1-Hz signal, you slap a divide-by-10 counter onto the output of the divide-by-6 counter.

Another approach used to create multidigit counters is to use a multidigit counter/display driver IC. One such IC is the ICM7217, a four-digit LED display programmable up/down counter made by Intersil. This device is typically used in hardwired applications where thumbwheel switches are used to load data and SPDT switches are used to control the chip. The ICM7217A provides multiplexed seven-segment LED display outputs that are used to drive common cathode displays.

A simple application of the ICM7217A is a four-digit unit counter shown in Fig. 12.96. If you are interested in knowing all the specifics of how this counter works, along with learning about other applications for this device, check out Maxim’s data sheets at It is better to learn from the maker in this case. Also, take a look at the other counter/display driver ICs Maxim has to offer. Other manufacturers produce similar devices, so visit their websites as well.


FIGURE 12.96

12.8 Shift Registers

Data words traveling through a digital system frequently must be temporarily held, copied, and bit-shifted to the left or to the right. A device that can be used for such applications is the shift register. A shift register is constructed from a row of flip-flops connected so that digital data can be shifted down the row either in a left or right direction. Most shift registers can handle parallel movement of data bits as well as serial movement, and also can be used to convert from parallel to serial or from serial to parallel. Figure 12.97 shows several types of shift register arrangements: serial-in/serial-out, parallel-in/serial-out, and serial-in/parallel out.


FIGURE 12.97

12.8.1 Serial-In/Serial-Out Shift Registers

Figure 12.98 shows a simple 4-bit serial-in/serial-out shift register made from D flip-flops. Serial data is applied to the D input of flip-flop 0. When the clock line receives a positive clock edge, the serial data is shifted to the right from flip-flop 0 to flip-flop 1. Whatever bits of data were present at flip-flop 2’s, 3’s, and 4’s outputs are shifted to the right during the same clock pulse. To store a 4-bit word into this register requires four clock pulses. The rightmost circuit shows how you can rewire the flip-flops to make a shift-left register. To make larger bit-shift registers, more flip-flops are added (for example, an 8-bit shift register would require eight flip-flops cascaded together).


FIGURE 12.98

12.8.2 Serial-In/Parallel-Out Shift Registers

Figure 12.99 shows a 4-bit serial-in/parallel-out shift register constructed from D flip-flops. This circuit is essentially the same as the previous serial-in/serial-out shift register, except now you attach parallel output lines to the outputs of each flip-flop as shown. Note that this shift register circuit also comes with an active-low clear input and a strobe input that acts as a clock enable control. The timing diagram in the figure shows a sample serial-to-parallel shifting sequence.


FIGURE 12.99

12.8.3 Parallel-In/Serial-Out Shift Registers

Constructing a 4-bit parallel-to-serial shift register from D flip-flops requires some additional control logic, as shown in the circuit in Fig. 12.100. Parallel data must first be loaded into the D inputs of all four flip-flops. To load data, the SHIFT/ is made low. This enables the AND gates with X marks, allowing the 4-bit parallel input word to enter the D0-D3 inputs of the flip-flops. When strobe and CLK are both high, the 4-bit parallel word is latched simultaneously into the four flip-flops and appears at the Q0-Q3 outputs. To shift the latched data out through the serial output, the SHIFT/ line is made high. This enables all unmarked AND gates, allowing the latched data bit at the Q output of a flip-flop to pass (shift) to the D input of the flip-flop to the right. In this shift mode, four clock pulses are required to shift the parallel word out of the serial output.


FIGURE 12.100

12.8.4 Ring Counter (Shift Register Sequencer)

The ring counter (shift register sequencer) is a unique type of shift register that incorporates feedback from the output of the last flip-flop to the input of the first flip-flop. Figure 12.101 shows a 4-bit ring counter made from D-type flip-flops. In this circuit, when the input is set low, Q0 is forced high by the active-low preset, while Q1, Q2, and Q3 are forced low (cleared) by the active-low clear. This causes the binary word 1000 to be stored within the register. When the line is brought low, the data bits stored in the flip-flops are shifted right with each positive clock edge. The data bit from the last flip-flop is sent to the D input of the first flip-flop. The shifting cycle will continue to recirculate while the clock is applied. To start a fresh cycle, the line is momentarily brought low.


FIGURE 12.101

12.8.5 Johnson Shift Counter

The Johnson shift counter is similar to the ring counter except that its last flip-flop feeds data back to the first flip-flop from its inverted output ( ). For this reason, this type is sometimes called a Moebius counter, as the bit sequence will be shifted out first “normally,” then inverted, then normally, and so on. In the simple 4-bit Johnson shift counter shown in Fig. 12.102, you start out by applying a low to the line, which sets presets Q0 high; Q1, Q2, and Q3low; and high. In other words, you load the register with the binary word 1000, as you did with the ring counter.


FIGURE 12.102

Now, when you bring the line low, data will shift through the register. However, unlike the ring counter, the first bit sent back to the D0 input of the first flip-flop will be high because feedback is from not Q3. At the next clock edge, another high is fed back to D0; at the next clock edge, another high is fed back; at the next edge, another high is fed back. Only after the fourth clock edge does a low get fed back (the 1 has shifted down to the last flip-flop and goes high). At this point, the shift register is full of 1s.

As more clock pulses arrive, the feedback loop supplies lows to D0 for the next four clock pulses. After that, the Q outputs of all the flip-flops are low, while goes high. This high from is fed back to during the next positive clock edge, and the cycle repeats.

As you can see, the 4-bit Johnson shift counter has eight output stages (which require eight clock pulses to recycle), not four, as is the case with the ring counter.

12.8.6 Shift Register ICs

Now that we have covered the basic theory of shift registers, let’s take a look at practical shift register ICs that contain all the necessary logic circuitry inside. It is not uncommon for a serial to parallel shift register IC to be used with a microcontroller to provide it with more outputs when driving LEDs. The serial data is fed into the shift register and then the output latched to turn the LEDs on or off.

7491A 8-Bit Serial-In/Serial-Out Shift Register IC

The 7491A is an 8-bit serial-in/serial-out shift register that consists of eight internally linked SR flip-flops. This device has positive edge-triggered inputs and a pair of data inputs (A and B) that are internally ANDed together, as shown in the logic diagram in Fig. 12.103. This type of data input means that for a binary 1 to be shifted into the register, both data inputs must be high. For a binary 0 to be shifted into the register, either input can be low. Data is shifted to the right at each positive clock edge.


FIGURE 12.103

74164 8-Bit Serial-In/Parallel-Out Shift Register IC

The 74164 is an 8-bit serial-in/parallel-out shift register. It contains eight internally linked flip-flops and has two serial inputs, Dsa and Dsb, which are ANDed together. Like the 7491A, the unused serial input acts as an enable/disable control for the other serial input. For example, if you use Dsa as the serial input, you must keep Dsb high to allow data to enter the register, or you can keep it low to prevent data from entering the register.

Data bits are shifted one position to the right at each positive clock edge. The first data bit entered will end up at the Q7 parallel output after the eighth clock pulse. The master reset resets all internal flip-flops and forces the Q outputs low when it is pulsed low.

In the sample circuit shown in Fig. 12.104, a serial binary number 10011010 (15410) is converted into its parallel counterpart. Note the AND gate and strobe input used in this circuit. The strobe input acts as a clock enable input; when it is set high, the clock is enabled. The timing diagram paints the rest of the picture.


FIGURE 12.104

75165 8-Bit Serial-In or Parallel-In/Serial-Out Shift Register IC

The 75165 is a unique 8-bit device that can act as either a serial-to-serial shift register or as a parallel-to-serial shift register. When used as a parallel-to-serial shift register, parallel data is applied to the D0-D7 inputs and then loaded into the register when the parallel load input is pulsed low. To begin shifting the loaded data out of the serial output Q7 (or if you want inverted bits), the clock enable input must be set low to allow the clock signal to reach the clock inputs of the internal D-type flip-flops. When used as a serial-to-serial shift register, serial data is applied to the serial data input DS. A sample shift, load, and inhibit timing sequence is shown in Fig. 12.105.


FIGURE 12.105

74194 Universal Shift Register IC

Figure 12.106 shows the 74194 4-bit bidirectional universal shift register. This device can accept either serial or parallel inputs, provide serial or parallel outputs, and shift left or right based on input signals applied to select controls S0 and S1. Serial data can be entered into either the serial shift-right input (DSR) or the serial shift-left input (DSL). Select controls S0 and S1 are used to initiate a hold (S0 = low, S1 = low), shift left (S0 = low, S1 = high), shift-right (S0= high, S1 = low), or to parallel load (S0 = high, S1 = high) mode. A clock pulse must then be applied to shift or parallel load the data.


FIGURE 12.106

In parallel load mode (S0 and S1 are high), parallel input data is entered via the D0 through D3 inputs and transferred to the Q0 to Q3 outputs following the next low-to-high clock transition. The 74194 also has an asynchronous master reset input that forces all Q outputs low when pulsed low. To make a shift-right recirculating register, the Q3 output is wired back to the DSR input, while making S0 = high and S1 = low. To make a shift-left recirculating register, the Q0 output is connected back to the DSL input, while making S0 = low and S1 = high. The timing diagram in Fig. 12.106 shows a typical parallel load and shifting sequence.

74299 8-Bit Universal Shift/Storage Register with Three-State Interface

A number of shift registers have three-state outputs—outputs that can assume a high, low, or high impedance state (open-circuit or float state). These devices are commonly used as storage registers in three-state bus interface applications.

An example 8-bit universal shift/storage register with three-state outputs is the 74299, shown in Fig. 12.107. This device has four synchronous operating modes that are selected via two select inputs, S0 and S1. Like the 74194 universal shift register, the 74299’s select modes include shifting right, shifting left, holding, and parallel loading (see the function table in Fig. 12.107). The mode-select inputs, serial data inputs (DS0 and DS7), and parallel-data inputs (I/O0 through I/O7) are positive edge triggered. The master reset input is an asynchronous active-low input that clears the register when pulsed low.


FIGURE 12.107

The three-state bidirectional I/O port has three modes of operation:

· The read-register mode allows data within the register to be available at the I/O outputs. This mode is selected by making both output-enable inputs ( and ) low and making one or both select inputs low.

· The load-register mode sets up the register for a parallel load during the next low-to-high clock transition. This mode is selected by setting both select inputs high.

· The disable-I/O mode acts to disable the outputs (set to a high impedance state) when a high is applied to one or both of the output-enable inputs. This effectively isolates the register from the bus to which it is attached.

12.8.7 Simple Shift Register Applications

16-Bit Serial-to-Parallel Converter

A simple way to create a 16-bit serial-to-parallel converter is to join two 74164 8-bit serial-in/parallel-out shift registers, as shown in Fig. 12.108. To join the two ICs, simply wire the Q7 output from the first register to one of the serial inputs of the second register. (Recall that the serial input that is not used for serial input data acts as an active-high enable control for the other serial input.)


FIGURE 12.108

In terms of operation, when data is shifted out of Q7 of the first register (or data output D7), it enters the serial input of the second (the example uses DSa as the serial input) and will be presented to the Q0 output of the second register (or data output D8). For an input data bit to reach the Q7 output of the second register (or data output D15), 16 clock pulses must be applied.

8-Bit Serial-to-Parallel Converter with Simultaneous Data Transfer

Figure 12.109 shows a circuit that acts as a serial-to-parallel converter that outputs the converted 8-bit word only when all 8 bits have been entered into the register. Here, a 74164 8-bit serial-in/parallel-out shift register is used, along with a 74HCT273 octal D-type flip-flop and a divide-by-8 counter. At each positive clock edge, the serial data is loaded into the 74164. After eight clock pulses, the first serial bit entered is shifted down to the 74164’s Q7 output, while the last serial bit entered resides at the 74164’s Q0 output. At the negative edge of the eighth clock pulse, the negative-edge triggered divide-by-8 circuit’s output goes high. During this high transition, the data present on the inputs of the 74HCT273 (which hold the same data present at the 74164’s Q outputs) is passed to the 74HCT273’s outputs at the same time. (Think of the 74HCT273 as a temporary storage register that dumps its contents after every eighth clock pulse.)


FIGURE 12.109

8-Bit Parallel-to-Serial Interface

Figure 12.110 shows a 74165 8-bit parallel-to-serial shift register used to accept a parallel ASCII word and convert it into a serial ASCII word that can be sent to a serial device. Recall that ASCII codes are only 7 bits long (for example, the binary code for & is 010 0110). How do you account for the missing bit? As it turns out, most 8-bit devices communicating via serial ASCII will use an additional eighth bit for a special purpose, perhaps to act as a parity bit or as a special function bit to enact a special set of characters. Often, the extra bit is simply set low and ignored by the serial device receiving it.


FIGURE 12.110

To keep things simple, let’s set the extra bit low and assume that is how the serial device likes things done. This means that you will set the D0 input of the 74165 low. The MSB of the ASCII code will be applied to the D1 input, while the LSB of the ASCII code will be applied to the D7 input. Now, with the parallel ASCII word applied to the inputs of the register, when you pulse the parallel load line ( ) low, the ASCII word, along with the “ignored bit,” is loaded into the register. Next, you must enable the clock to allow the loaded data to be shifted out serially, by setting the clock enable input ( ) low for the duration it takes for the clock pulses to shift out the parallel word. After the eighth clock pulse (0 to 7), the serial device will have received all 8 serial data bits. Practically speaking, a microprocessor or microcontroller is necessary to provide the and lines with the necessary control signals to ensure that the register and serial device communicate properly.

Recirculating Memory Registers

A recirculating memory register is a shift register that is preloaded with a binary word that is serially recirculated through the register via a feedback connection from the output to the input. Recirculating registers can be used for a number of applications, from supplying a specific repetitive waveform used to drive IC inputs to driving output drivers used to control stepper motors.

In the leftmost circuit in Fig. 12.111, a parallel 4-bit binary word is applied to the D0 to D3 inputs of a 74194 universal shift register. When the S1 select input is brought high (switch opened), the 4-bit word is loaded into the register. When the S1 input is then brought low (switch closed), the 4-bit word is shifted in a serial fashion through the register, out Q3, and back to Q0 via the DSR input (serial shift-right input) as positive clock edges arrive. Here, the shift register is loaded with 0111. As you begin shifting the bits through the register, a single low output will propagate down through high outputs, which in turn causes the LED attached to the corresponding low output to turn on. In other words, you have made a simple Christmas tree flasher.


FIGURE 12.111

The rightmost circuit in Fig. 12.111 is basically the same thing as the leftmost circuit. However, now the circuit is used to drive a stepper motor. Typically, a stepper motor has four stator coils that must be energized in sequence to make the motor turn at a given angle. For example, to make a simple stepper motor turn clockwise, you must energize its stator coils 1, 2, 3, and 4 in the following sequence: 1000, 0100, 0010, 0001, 1000, and so on. To make the motor go counterclockwise, apply the following sequence: 1000, 0001, 0010, 0100, 1000, and so on. You can generate these simple firing sequences with the 74194 by parallel loading the D0 to D3 inputs with the binary word 1000. To output the clockwise firing sequence, simply shift bits to the right by setting S0 = high and S1 = low. As clock pulses arrive, the 1000 present at the outputs will then become 0100, then 0010, 0001, 1000, and so on.

The speed of rotation of the motor is determined by the clock frequency. To output the counterclockwise firing sequence, simply shift bits to the left by setting S0 = low and S1 = high. To drive steppers, it is typically necessary to use a buffer/driver interface like the 7407 shown in Fig. 12.111, as well a number of output transistors, not shown. Also, different types of stepper motors may require different firing sequences than the one shown here. Stepper motors and the various circuits used to drive them are discussed in detail in Chap. 15.

12.9 Analog/Digital Interfacing

A number of tricks are used to interface analog circuits with digital circuits. In this section, we’ll take a look at two basic levels of interfacing. One level deals with simple on/off triggering. The other level deals with true analog-to-digital and digital-to-analog conversion—converting analog signals into digital numbers and converting digital numbers into analog signals. These techniques are just as applicable to connecting things to the digital input pins of a microcontroller.

12.9.1 Triggering Simple Logic Responses from Analog Signals

There are times when you need to drive logic from simple on/off signals generated by analog devices. For example, you may want to latch an alarm (via a flip-flop) when an analog voltage—say, one generated from a temperature sensor—reaches a desired threshold level. Or perhaps you simply want to count the number of times a certain analog threshold is reached. For simple on/off applications such as these, it is common to use a comparator or op amp as the interface between the analog output of the transducer and the input of the logic circuit. Often it is possible to simply use a voltage divider network composed of a transducer of variable resistance and a pullup resistor. Figure 12.112 shows some sample networks to illustrate the point.


FIGURE 12.112

In Fig. 12.112a, a phototransistor is used to trigger a logic response. Normally, the phototransistor is illuminated, which keeps the input of the first Schmitt inverter low. The output of the second inverter is high. When the light is briefly interrupted, the phototransistor momentarily stops conducting, causing the input to the first inverter to pulse low, while the output of the second inverter pulses high. This high pulse could be used to latch a D flip-flop, which could be used to trigger an LED or a buzzer alarm.

In Fig. 12.112b, a single-supply comparator with open-collector output is used as an analog-to-digital interface. When an analog voltage applied to Vin exceeds the reference voltage (Vref) set at the noninverting input (+) via the pot, the output goes low (the comparator sinks current through itself to ground). When Vin goes below Vref, the output goes high (the comparator’s output floats, but the pullup resistor pulls the comparator’s output high).

In Fig. 12.112c, a simple application of the previous comparator interface is shown. The input voltage is generated by an LM34 or LM35 temperature sensor. The LM34 generates 10 mV/°F, while the LM35 generates 10 mV/°C. The resistance of the pot and V+ determine the reference voltage. If we want to drive the comparator low when 75°C is reached, we set the reference voltage to 750 mV, assuming we’re using the LM35.

In Fig. 12.112d, an op amp set in comparator mode can also be used as an analog-to-digital interface for simple switching applications. CMOS logic can be driven directly through a current limiting resistor, as shown. If the supply voltage of the op amp exceeds the supply voltage of the logic, protection diodes should be used (as shown in the figure).

Protection diodes were not necessary with the LM339 because that has open-collector outputs.

In Fig. 12.112e, an op amp that is used to drive TTL typically uses a transistor output stage like the one shown here. The diode acts to prevent base-to-emitter reverse breakdown. When Vin exceeds Vref, the op amp’s output goes low, the transistor turns off, and the logic input receives a high.

In Fig. 12.112f, an n-channel MOSFET transistor is used as an output stage to an op amp.

12.9.2 Using Logic to Drive External Loads

Driving simple loads such as LEDs, relays, buzzers, or any device that assumes either an on or off state is relatively simple. When driving such loads, it is important to first check the driving logic’s current specifications—how much current, say, a gate can sink or source. After that, you determine how much current the device to be driven will require. If the device draws more current than the logic can source or sink, a high-power transistor typically can be used as an output switch. Figure 12.113 shows some sample circuits used to drive various loads.


FIGURE 12.113

In Fig. 12.113a, LEDs can be driven directly by logic through a current-limiting resistor. Current can either be sourced or sunk. If an LED requires more current than the logic can supply or sink, a transistor output stage like the one shown in Fig. 12.113f can be used.

Figure 12.113b shows a simple way to get dual-lighting action from a pair of LEDs. When the gate’s output goes low, the upper green LED turns on, while the lower red LED turns off. The LEDs switch states when the output goes high.

Relays will draw considerable current. To avoid damaging the logic device, in Fig. 12.113c, a power MOSFET transistor is attached to the logic output. The diode is used to protect the circuit from current spikes generated by relay as it switches states.

A handy method for interfacing standard logic with loads is to use a gate with an open-collector output as a go-between. Recall that open-collector gates cannot source current; they can only sink current. However, they typically can sink ten times the current of a standard logic gate. In Fig. 12.113d, an open-collector gate is used to drive a relay. Check the current ratings of specific open-collector devices before using them to be sure they can handle the load current.

Figure 12.113e shows another open-collector application. In Fig. 12.113f, a bipolar transistor is used to increase the output drive current used to drive a high-current LED. Make sure the transistor is of the proper current rating.

Figure 12.113g is basically the same as the previous example, but the load can be something other than an LED.

In Fig. 12.113h, an optocoupler is used to drive a load that requires electrical isolation from the logic driving it. Electrical isolation is often used in situations where external loads use a separate ground system. The voltage level at the load side of the optical interface can be set via VCC. There are many different types of optocouplers available (see Chap. 5).

12.9.3 Analog Switches

Analog switches are ICs designed to switch analog signals via digital control. The internal structure of these devices typically consists of a number of logic control gates interfaced with transistor stages used to control the flow of analog signals.

Figure 12.114 shows various types of analog switches. The CMOS 4066B quad bilateral switch uses a single-supply voltage from 3 to 15 V. It can switch analog or digital signals within ±7.5 V and has a maximum power dissipation of around 700 mW. Individual switches are controlled by digital inputs A through D. The TTL-compatible AH0014D DPDT analog switch can switch analog signals of ±10 V via the A and B logic control inputs. Note that this device has separate analog and digital supplies: V+ and V− are analog; VCC and GND are digital. The DG302A dual-channel CMOS DPST analog switch can switch analog signals within the ±10-V range at switching speeds up to 15 ns.


FIGURE 12.114

A number of circuits use analog switches. They are found in modulator/demodulator circuits, digitally controlled frequency circuits, analog signal-gain circuits, and analog-to-digital conversion circuits, where they often act as sample-hold switches. They can, of course, be used simply to turn a given analog device on or off.

12.9.4 Analog Multiplexer/Demultiplexer

Recall from Sec. 12.3 that a digital multiplexer acts like a data selector, while a digital demultiplexer acts like a data distributor. Analog multiplexers and demultiplexers act the same way but are capable of selecting or distributing analog signals. (They still use digital select inputs to select which pathways are open and which are closed to signal transmission.)

A popular analog multiplexer/demultiplexer IC is the 4051B, shown in Fig. 12.115. This device functions as either a multiplexer or demultiplexer, since its inputs and outputs are bidirectional (signals can flow in either direction). When used as a multiplexer, analog signals enter through I/O lines 0 through 7, while the digital code that selects which input is passed to the analog O/I line (pin 3) is applied to digital inputs A, B, and C. See the truth table in the figure. When used as a demultiplexer, the connections are reversed: The analog input comes in through the analog O/I line (pin 3) and passes out through one of the seven analog I/O lines. The specific output is again selected by the digital inputs A, B, and C. Note that when the inhibit line (INH) is high, none of the addresses are selected.


FIGURE 12.115

The I/O analog voltage levels for the 4051B are limited to a region between the positive supply voltage VDD and the analog negative supply voltage VEE. Note that the VSS supply is grounded. If the analog signals you are planning to use are all positive, VEE and VSS can both be connected to a common ground. However, if you plan to use analog voltages that range from, say, −5 to +5 V, VEE should be set to −5 V, while VDD should be set to +5 V. The 4051B accepts digital signals from 3 to 15 V, while allowing for analog signals from −15 to +15 V.

12.9.5 Analog-to-Digital and Digital-to-Analog Conversion

In order for analog devices (temperature sensors, strain gauges, position sensors, light meters, and so on) to communicate with digital circuits in a manner that goes beyond simple threshold triggering, we use an analog-to-digital converter (ADC). An ADC converts an analog signal into a series of binary numbers, each number proportional to the analog level measured at a given moment. Typically, the digital words generated by the ADC are fed into a microprocessor or microcontroller, where they can be processed, stored, interpreted, and manipulated. Analog-to-digital conversion is used in data-acquisition systems, digital sound recording, and within simple digital display test instruments (such as light meters and thermometers).

In order for a digital circuit to communicate with the analog world, we use a digital-to-analog converter (DAC). A DAC takes a binary number and converts it to an analog voltage that is proportional to the binary number. By supplying different binary numbers, one after the other, a complete analog waveform is created. DACs are commonly used to control the gain of an op amp, which in turn can be used to create digitally controlled amplifiers and filters. They are also used in waveform generator and modulator circuits and as trimmer replacements, and are found in a number of process-control and autocalibration circuits.

Many digital consumer products such as MP3 players, DVDs, and CD players use digital signal processing ADCs and DACs often contained in a microcontroller.

ADC and DAC Basics

Figure 12.116 shows the basic idea behind analog-to-digital and digital-to-analog conversion. In the analog-to-digital figure, the ADC receives an analog input signal along with a series of digital sampling pulses. Each time a sampling pulse is received, the ADC measures the analog input voltage and outputs a 4-bit binary number that is proportional to the analog voltage measured during the specific sample. With 4 bits, we get 16 binary codes (0000 to 1111) that correspond to 16 possible analog levels (for example, 0 to 15 V).


FIGURE 12.116

In the digital-to-analog conversion figure, the DAC receives a series of 4-bit binary numbers. The rate at which new binary numbers are fed into the DAC is determined by the logic that generates them. With each new binary number, a new analog voltage is generated. As with the ADC example, we have a total of 16 binary numbers to work with and 16 possible output voltages.

As you can see from the graphs, both these 4-bit converters lack the resolution needed to make the analog signal appear continuous (without steps). To make things appear more continuous, a converter with higher resolution is used. This means that instead of using 4-bit binary numbers, we use larger-bit numbers, such as 6-bit, 8-bit, 10-bit, 12-bit, 16-bit, or even 18-bit or higher numbers. If our converter has a resolution of 8 bits, we have 28 = 256 binary numbers to work with, along with 256 analog steps. Now, if this 8-bit converter is set up to generate 0 V at binary 00000000 and 15 V at binary 11111111 (full scale), then each analog step is only 0.058 V high (1256 × 15 V). With an 18-bit converter, the steps get incredibly tiny because we have 218 = 262,144 binary numbers and steps. With 0 V corresponding to binary 000000000000000000 and 15 V corresponding to 111111111111111111, the 18-bit converter yields steps that are only 0.000058 V high! As you can see in the 18-bit case, the conversion process between digital and analog appears practically continuous.

Simple Binary-Weighted DAC

Figure 12.117 shows a simple 4-bit DAC that is constructed from a digitally controlled switch (74HC4066), a set of binary-weighted resistors, and an operational amplifier. The basic idea is to create an inverting amplifier circuit whose gain is controlled by changing the input resistance Rin. The 74HC4066 and the resistors together act as a digitally controlled Rin that can take on one of 16 possible values. You can think of the 74HC4066 and resistor combination as a digitally controlled current source. Each new binary code applied to the inputs of the 74HC4066 generates a new discrete current level that is summed by RF to provide a new discrete output voltage level.


FIGURE 12.117

We choose scaled resistor values of R, R/2, R/4, and R/8 to give Rin discrete values that are equally spaced. To find all possible values of Rin, we use the formula provided in Fig. 12.117. This formula looks like the old resistors-in-parallel formula, but we must exclude those resistors that are not selected by the digital input code—that’s what the coefficients A through D are for (a coefficient is either 1 or 0, depending on the digital input).

To find the analog output voltage, we simply use Vout = −Vref(RF/Rin)—the expression used for the inverting amplifier (see Chap. 8). Figure 12.117 shows what we get when we set Vref = −5 V, R = 100 kΩ, and RF = 20 kΩ, and take all possible input codes.

The binary-weighted DAC shown in Fig. 12.117 is limited in resolution (4-bit, 16 analog levels). To double the resolution (make an 8-bit DAC), you might consider adding another 74HC4066 and R/16, R/32, R/64, and R/128 resistors. In theory, this works; in reality, it doesn’t. The problem with this approach is that when we reach the R/128 resistor, we must find a 0.78125-kΩ resistor, assuming R = 100 kΩ. Assuming we can find or construct an equivalent resistor network for R/128, we’re still in trouble because the tolerances of these resistors will cause problems. This scaled-resistor approach becomes impractical when we deal with resolutions of more than a few bits. To increase the resolution, we scrap the scaled-resistor network and replace it with an R/2R ladder network. The manufacturers of DAC ICs do this as well.

R/2R Ladder DAC

An R/2R DAC uses an R/2R resistor ladder network instead of a scaled-resistor network, as was the case in the previous DAC. The benefit of using the R/2R ladder is that we need only two resistor values: R and 2R. Figure 12.118 shows a simple 4-bit R/2R DAC. For now, assume that the switches are digitally controlled (in real DACs, they are replaced with transistors).


FIGURE 12.118

The trick to understanding how the R/2R ladder works is realizing that the current drawn through any one switch is always the same, no matter if it is thrown up or down. If a switch is thrown down, current will flow through the switch into ground (0 V). If a switch is thrown up, current will flow toward virtual ground—located at the op amp’s inverting input (recall that if the noninverting input of an op amp is set to 0 V, the op amp will make the inverting input 0 V, via negative feedback). Once you realize that the current through any given switch is always constant, you can figure that the total current (I) supplied by Vref will be constant as well. Once you have that, you figure out what fractions of the total current pass through each of the branches within the R/2R network using simple circuit analysis. Figure 12.118 shows that ½I passes through S3 (MSB switch), ¼I through S2, ⅛I through S1, and 116I through S0 (LSB switch). If you’re interested in how that was figured out, the circuit reduction shown in Fig. 12.119 should help.


FIGURE 12.119

Now that we have a means of consistently generating fractions of 12I, 14I, 18I, and 116I, we can choose, via the digital input switches, which fractions are summed together by the amplifier. For example, if switches S3, S2, S1, and S0 are thrown to 0101 (5), 14 I + 116 I combine to form Isum. But what is I? Using Ohm’s law, it’s just I = Vref / R = +5 V / 10 kΩ = 500 µA. This means that Isum = 14(500 µA) + 116(500 µA) = 156.25 µA. The final output voltage is determined by Vout = −IsumRF = − (156.25 µA)(20 kΩ) = −3.125 V. The formulas and the table in Fig. 12.118 show the other possible binary/analog combinations.

To create an R/2R DAC with higher resolution, we simply add more runs and switches to the ladder.

Integrated DACs

Often, making DACs from scratch isn’t worth the effort. The cost as well as the likelihood for conversion errors is great. The best thing to do is to simply buy a DAC IC. You can buy these devices from a number of different manufacturers (such as National Semiconductor, Analog Devices, and Texas Instruments). The typical resolutions for these ICs are 6, 8, 10, 12, 16, and 18 bits. DAC ICs also may come with a serial digital input, as opposed to the parallel input scheme shown in Figs 12.117 and 12.118. Before a serial-input DAC can make a conversion, the entire digital word must be clocked into an internal shift register.

Most often, DAC ICs come with an external reference input that is used to set the analog output range. There are some DACs that have fixed references, but these are becoming rare.

Often, you’ll see a manufacturer list one of its DACs as being a multiplying DAC. A multiplying DAC can produce an output signal that is proportional to the product of a varying input reference level (voltage or current) times a digital code. As it turns out, most DACs, even those that are specifically designated as multiplying DAC on the data sheets, can be used for multiplying purposes simply by using the reference input as the analog input. However, many such ICs do not provide the same quality multiplying characteristics, such as a wide analog input range and fast conversion times, as those that are called multiplying DACs.

Multiplying is most commonly applied in systems that use ratiometeric transducers (for example, position potentiometers, strain gauges, and pressure transducers). These transducers require an external analog voltage to act as a reference level on which to base analog output responses. If this reference level is altered, say, by an unwanted supply surge, the transducer’s output will change in response, and this results in conversion errors at the DAC end. However, if we use a multiplying DAC, we eliminate these errors by feeding the transducer’s reference voltage to the DAC’s analog input. If any supply voltage/current errors occur, the DAC will alter its output in proportion to the analog error.

DACs are capable of producing unipolar (single-polarity output) or bipolar (positive and negative) output signals. In most cases, when a DAC is used in unipolar mode, the digital code is expressed in standard binary. When used in bipolar mode, the most common code is either offset binary or 2’s complement. Offset binary and 2’s complement codes make it possible to express both positive and negative values. Figure 12.120 shows all three codes and their corresponding analog output levels (referenced from an external voltage source).

Common Digital Codes Used by DACs


FIGURE 12.120

Note that in the figure, FS stands for full scale, which is the maximum analog level that can be reached when applying the highest binary code. It is important to realize that at full scale, the analog output for an n-bit converter is actually (2n − 1) / 2n × Vref, not 2n/2n × Vref. For example, for an 8-bit converter, the number of binary numbers is 28 = 256, while the maximum analog output level is 255/256 Vref, not 256/256 Vref, since the highest binary number is 255 (1111 1111). The “missing count” is used up by the LSB-1 condition (0 state).

Example DAC ICs


The DAC0808 (National Semiconductor) is a popular 8-bit DAC that requires an input reference current and supplies 1 of 256 analog output current levels. Figure 12.121 shows a block diagram of the DAC0808, along with its IC pin configuration and a sample application circuit.


FIGURE 12.121

In the application circuit, the analog output range is set by applying a reference current (Iref) to pin 14 (+Vref). In this example, Iref is set to 2 mA via an external +10 V/5 kΩ resistor combination. Note that another 5-kΩ resistor is required between pin 15 (−Vref) and ground.

To determine the DAC’s analog output current (Iout) for all possible binary inputs, we use the following formula:

At full scale (all A’s high or binary 255), Iout = Iref (255/256) = (2 mA)(0.996) = 1.99 mA. Considering that the DAC has 256 analog output levels, we can figure that each corresponding level is spaced 1.99 mA/256 = 0.0078 mA apart.

To convert the analog output currents into analog output voltages, we attach the op amp. Using the op amp rules from Chap. 8, we find that the output voltage is Vout = Iout × Rf. At full scale, Vout = (1.99 mA)(5 kΩ) = 9.95 V. Each analog output level is spaced 9.95 V/256 = 0.0389 V apart.

The DAC0808 can be configured as a multiplying DAC by applying the analog input signal to the reference input. In this case, however, the analog input current should be limited to a range from 16 µA to 4 mA to retain reasonable accuracy. See the National Semiconductor’s data sheets for more details.


The DAC8083A (Analog Devices) is a high-precision 12-bit CMOS multiplying DAC that comes with a serial digital input. Figure 12.122 shows a block diagram, pin configuration, and write cycle timing diagram for this device.


FIGURE 12.122

Before the DAC8043 can make a conversion, serial data must be clocked into the input register by supplying an external clock signal (each positive edge of the clock load one bit). Once loaded, the input register’s contents are dumped off to the DAC register by applying a low pulse to the line. Data in the DAC register is then converted to an output current through the Iout terminal.

In most applications, this current is then transformed into a voltage by an op amp stage, as is the case within the two circuits shown in Fig. 12.123. In the unipolar (two-quadrant) circuit, a standard binary code is used to select from 4096 possible analog output levels. In the bipolar (four-quadrant) circuit, an offset binary code is used again to select from 4096 analog output levels, but now the range is broken up to accommodate both positive and negative polarities.


FIGURE 12.123

If you’re interested in learning more about the DAC8043, go to Analog Device’s website and check out the data sheet.

Another very similar device worth considering is the MAX522.

12.9.6 Analog-to-Digital Converters

There are a number of techniques used to convert analog signals into digital signals. The most popular techniques include successive approximation conversion and parallel-encoded conversion (or flash conversion). Other techniques include half-flash conversion, delta-sigma processing, and pulse-code modulation (PCM). In this section, we’ll focus on the successive approximation and parallel-encoded conversion techniques. Most microcontrollers will have built-in ADC channels using one of the techniques described here.

Successive Approximation

Successive approximation analog-to-digital conversion is the most common approach used in integrated ADCs. In this conversion technique, each bit of the binary output is found, one bit at a time—MSB first. This technique yields fairly fast conversion times (from around 10 to 300 µs) with a limited amount of circuitry. Figure 12.124 shows a simple 8-bit successive approximation ADC, along with an example analog-to-digital conversion sequence.


FIGURE 12.124

To begin a conversion, the (start conversion) input is pulsed low. This causes the successive approximation register (SAR) to first apply a high on the MSB (D7) line of the DAC. With only D7 high, the DAC’s output is driven to one-half its full-scale level, which in this case is +5 V because the full-scale output is +10 V. The +5-V output level from the DAC is then compared with the analog input level, via the comparator. If the analog input level is greater than +5 V, the SAR keeps the D7 line high; otherwise, the SAR returns the D7 line low. At the next clock pulse, the next bit (D6) is tried. Again, if the analog input level is larger than the DAC’s output level, D6 is left high; otherwise, it is returned low.

During the next six clock pulses, the rest of the bits are tried. After the last bit (LSB) is tried, the CC (conversion complete) output of the SAR goes low, indicating that a valid 8-bit conversion is complete, and the binary data is ready to be clocked into the octal flip-flop, where it can be presented to the Q0-Q7 outputs.

The timing diagram shows a 3.8652-V analog level being converted into an approximate digital equivalent. Note that after the first approximation (the D7 try), the percentage error between the actual analog level and corresponding digital equivalent is 29.360 percent. However, after the final approximation, the percentage error is reduced to only 0.051 percent.

Until now, we’ve assumed that the analog input to our ADC was constant during the conversion. But what happens when the analog input changes during conversion time? Errors result. The more rapidly the analog input changes during the conversion time, the more pronounced the errors will become. To prevent such errors, a sample-and-hold circuit is often attached to the analog input. With an external control signal, this circuit can be made to sample the analog input voltage and hold the sample while the ADC makes the conversion.

With the exception of very high-speed ADCs, separate ADC ICs are now largely redundant and have been replaced with microcontrollers containing 12-bit or higher ADC channels.

Parallel-Encoded Analog-to-Digital Conversion (Flash Conversion)

Parallel-encoded analog-to-digital conversion, or flash conversion, is perhaps the easiest conversion process to understand. To illustrate the basics behind parallel encoding (also referred to as simultaneous multiple comparator or flash converting), let’s take a look at the simple 3-bit converter in Fig. 12.125.


FIGURE 12.125

The set of comparators is the key feature to note in this circuit. Each comparator is supplied with a different reference voltage from the 1 kΩ voltage divider network. Since we’ve set up a +5V reference voltage, the voltage drop across each resistor within the voltage divider network is 0.625 V. From this, you can determine the specific reference voltages given to each comparator (see Fig. 12.125).

To convert an analog signal into a digital number, the analog signal is applied to all the comparators at the same time, via the common line attached to the inverting inputs of all the comparators. If the analog voltage is between, say, 2.500 and 3.125 V, only those comparators with reference voltage below 2.500 V will output a high. To create a 3-bit binary output, the eight comparator outputs are fed into an octal-to-binary priority encoder. A D latch also can be incorporated into the circuit to provide enable control of the binary output. The truth table should fill in the rest.

12.10 Displays

A number of displays can be interfaced with control logic to display numbers, letters, special characters, and graphics. Two popular displays that we’ll consider here include the light-emitting diode (LED) display and the liquid-crystal display (LCD).

12.10.1 LED Displays

LED displays come in three basic configurations: numeric (numbers), alphanumeric (numbers and letters), and dot-matrix forms (see Fig. 12.126). Numeric displays consist of seven LED segments. Each LED segment is given a letter designation, as shown in the figure. Seven-segment LED displays are most frequently used to generate numbers (0-9), but they also can be used to display hexadecimal (0-9, A, B, C, D, E, F). The 14-segment, 16-segment, and special 4 × 7 dot matrix displays are alphanumeric. The 5 × 7 dot matrix display is both alphanumeric and graphic—you can display unique characters and simple graphics. See Chap. 5 for information about other types of LED displays.


FIGURE 12.126

Direct Drive of Numeric LED Displays

Seven-segment LED displays come in two varieties: common anode and common cathode. Figure 12.128 shows single digital eight-segment (seven digit segments + decimal point) displays of both varieties.


FIGURE 12.127

To drive a given segment of a common anode display, current must be sunk out through the corresponding segment’s terminal. With the common cathode display, current must be sourced into the corresponding segment’s terminal. A simple way to drive these displays is to use BCD to seven-segment display decoder/drivers, like the ones show in the figure. Applying a BCD input character results in a decimal digit being displayed (e.g., 0101 applied to A0-A3, or A-D displays a “5”). The 74LS47 active-low open-collector outputs are suited for a common anode display, while the 74HC4511’s active-high outputs are suited for a common cathode display. Both ICs also come with extra terminals used for lamp testing and ripple blanking, as well as leading zero suppression (controlling the decimal point).


FIGURE 12.128

When driving a multidigit display, say, one with eight digits, the previous technique becomes awkward. It requires eight discrete decoder/driver ICs. One way to avoid this problem is to use a special direct-drive LED display driver IC.

For example, National Semiconductor’s MM5450, shown in Fig. 12.133, is designed to drive 4- or 5-digit alphanumeric common anode LED displays. It comes with 34 TTL-compatible outputs that are used to drive desired LED segments within a display. Each of these outputs can sink up to 15 mA. In order to specify which output lines are driven high or low, serial input data are clocked into the driver’s serial input. The serial data chain that is entered is 36 bits long. The first bit is a start bit (set to 1), and the remaining 35 bits are data bits. Each data bit corresponds to a given output data line that is used to drive a given LED segment within the display. At the thirty-sixth positive clock signal, a LOAD signal is generated that loads the 35 data bits into the latches (see the block diagram in Fig. 12.133). At the low state of the clock, a signal is generated that clears the shift register for the next set of data. You can learn more about the MM5450 at

Multiplexed LED Displays

Another technique used to drive multidigit LED displays involves multiplexing. Multiplexing can drastically reduce the number of connections needed between display and control logic. In a multiplexed display, digits share common segment lines. Also, only one digit within the display is lighted at a time. To make it appear that a complete readout is displayed, all the digits must be flashed very rapidly in sequence, over and over again. The simple example in Fig. 12.129 shows multiplexing in action.To reduce the component count further, you can do away with the 74HC4511 and just use 7 digital outputs from the microcontroller.


FIGURE 12.129

Here, we have a multiplexed common-cathode display—all digits share common segment lines (a-g). To supply a full one-digit readout, digits must be flashed rapidly, one at a time. To enable a given digit, the digit’s common line is grounded via one of the digital drivers (transistors)—all other digits’ common lines are left floating. In this example, the drivers are controlled by a microcontroller. To light the segments of a given digit, the microcontroller supplies the appropriate 4-bit BCD code to the seven-segment decoder/driver (74HC4511). As an example, if we wanted to display 1234, we would need to program the microcontroller (using software) to turn off all digits except the MSD (leftmost digit) and then supply the decoder/driver with the BCD code for 1. Then the next significant digit (2) would be driven, and then the next significant digit (3), and then the LSD (4). After that, the process would recycle for as long as we wanted our program to display 1234.

12.10.2 Liquid-Crystal Displays

In low-power CMOS digital systems (for example, battery- or solar-powered electronic devices), the dissipation of an LED display can consume most of a system’s power requirements, which is something you want to avoid, especially since you are looking to save power when using CMOSs. LCDs, on the other hand, are ideal for low-power applications.

Unlike an LED display, an LCD is a passive device. This means that instead of using electric current to generate light, it uses light that is already externally present (such as sunlight, room lighting). For the LCD’s optical effects to occur, the external light source needs to supply only a minute amount of power (within the mW/cm2 range).

Simple Alphanumeric Display


FIGURE 12.130

Figure 12.130 shows a common anode, 2-character, 14-segment (+ decimal) alphanumeric display. Notice that the segments of the two characters are internally wired together. This means that the display is designed for multiplexing. Though it is possible to use a microcontroller along with transistor drivers to control this display, the number of lines required is fairly large. Another option is to use a special driver IC, like Intersil’s ICM7243B 14-segment 6-bit ASCII driver. Another alternative is simply to avoid using this kind of display and use a “smart” alphanumeric display that contains all the necessary control logic (drivers, code converters, and so on).

“Smart” Alphanumeric Display


FIGURE 12.131

The HPDL-1414 is a “smart,” 4-character, 16-segment display. This device is complete with LEDs, on-board 4-word ASCII memory, a 64-word character generator, 17-segment drivers, 4-digit drivers, and scanning circuitry necessary to multiplex the four LED characters. It is TTL-compatible and relatively easy to use. The seven data inputs D0 to D6 accept a 7-bit ASCII code, while the digital select inputs A0 and A1 accept a 2-bit binary code that is used to specify which of the four digits is to be lighted. The WRITE input is used to load new data into memory. After a character has been written to memory, the IC decodes the ASCII data, drives the display, and refreshes it without the need for external hardware or software.

One disadvantage with LCDs is their slow switching speeds (the time it takes for a new digit/character to appear). Typical switching speeds for LCDs range from around 40 to 100 ms. At low temperatures, the switching speeds get even worse. Another problem with LCDs is the requirement that external light be present. Though there are LCD displays that come with backlighting (such as an LED behind the display), obviously, this will increase power consumption.

Basic Explanation of How an LCD Works

An LCD consists of a number of layers that include a polarizer, a set of transparent electrodes, a liquid-crystal element, a transparent back electrode, a second polarizer, and a mirror (see the leftmost illustration in Fig. 12.132).


FIGURE 12.132

The transparent top electrodes are used to generate the individual segments of a digit, character, and so on, while the transparent back electrode forms a common plane, often referred to as the back plane (BP). The top electrode segments and the back electrode are wired to external contacts. With no potential difference between a given top electrode and the back electrode, the region where the top electrode is located appears silver in color against a silver background. However, when a potential is applied between a given top electrode and back electrode, the region where the top electrode is located appears dark against a silver background.

The circuit in Fig. 12.132 shows a basic way to drive a seven-segment LCD. It uses a 74HC4511 BCD decoder and XOR gates to generate the prior drive signals for the LCD. A very important thing to note in this circuit is the clock. As it turns out, an LCD actually requires ac drive signals (for example, squarewaves) instead of dc drive signals. If dc were used, the primary component of the display—namely, the liquid crystal—would undergo electrochemical degradation (more on the liquid crystal in a moment). The optimal frequency of the applied ac drive signal is typically from around 25 Hz to a couple hundred hertz. Now that we understand that, it is easy to see why we need the XOR gates.

As the clock delivers squarewaves to the back electrode (back plane, or BP), the XOR gates act as enable gates that pass and invert a signal and apply it to a given top electrode segment. For example, if a BCD code of 1001 (5) is applied to the decoder, the decoder’s outputs a, c, d, f, and g go high, while outputs b and e go low. When a positive clock pulse arrives, XOR gates attached to the outputs that are high invert the high levels. XOR gates attached to outputs that are low pass on the low levels. During the same pulse duration, the back plane is set high. Potentials now are present between a, c, d, f, and g segments and the back plane, and therefore these segments appear dark. Segments b and e, along with the background, appear silverish because no potential exists between them and the back plane. Now, when the clock pulse goes low, the display remains the same (provided the BCD input hasn’t changed), since all that has occurred is a reverse in polarity. This has no effect on the optical properties of the display.

Detailed Explanation of How an LCD Works (the Physics)

Figure 12.133 shows how an LCD generates a clear (silverish) segment. When control signals sent to the transparent top and back electrodes are in phase, no potential exists between the two electrodes. With no potential present, the cigar-shaped organic liquid crystals (nematic crystals) arrange themselves in spiral state, as shown in the figure.


FIGURE 12.133

The upper crystal aligns itself horizontal to the page, while the lowest crystal aligns itself perpendicular to the page. The upper crystal and the lower crystal are held in place by tiny grooves that are etched into the inner surfaces of the glass surfaces of the cell. Crystals in between the upper crystal and the lower crystal progressively spiral 90° due to electrostatic forces that exist between neighboring crystals. When polarized light passes through a region of the display that contains these spirals, the polarization angle of the light is rotated 90°.

Now, looking at the display as a whole, when incident unpolarized light passes through polarizer 1 (as shown in the figure), the light becomes polarized in the same direction of the plane of polarization of the first polarizer. The polarized light then passes through the transparent top electrode and enters the liquid-crystal cell. As it passes through the cell, its polarization angle is rotated 90°. The polarized light that exits the cell then passes through the transparent back electrode and the second polarizer without problems. (If we were to remove the liquid-crystal cell, all polarized light that passed through the first polarizer would be absorbed, since we would have crossed polarizers.) The light that passes through the second polarizer then reflects off the mirror, passes through the second polarizer, on through the liquid-crystal cell (getting rotated 90°), through the first polarizer, and finally reaches the observer’s eye. This reflected light appears silver in color. Note that the background of LCDs constantly appears silver because no potential exists across the liquid-crystal cell in the background region.

Figure 12.134 shows how an LCD generates a dark segment. When control signals sent to the top and back electrodes are out of phase, a potential difference exists between the two electrodes. This causes the crystals to align themselves in a parallel manner, as shown in the figure. When the polarized light from the first polarizer passes through the cell region containing these parallel crystals, nothing happens—the polarization angle stays the same. However, when the light comes in contact with the second polarizer, it is absorbed because the angle of polarization of the light and the plane of polarization of the second polarizer are perpendicular to each other. Since light reaches the mirror, no light is reflected back to the observer’s eye, and hence the segment appears dark.


FIGURE 12.134

The LCD shown in Fig. 12.133 represents what is referred to as a standard twisted nematic display. Another common LCD is the supertwist nematic display. Unlike the standard twisted display, this display’s nematic crystals rotate 270° from top to bottom. The extra 180° twist improves the contrast and viewing angle.

Driving LCDs


The CD4543B (Texas Instruments), shown in Fig. 12.135, is a BCD-to-seven-segment latch/decoder/driver that is designed for LCDs, as well as for LED displays. When used to drive LCDs, a squarewave must be applied simultaneously to the CD4543B’s Phase (Ph) input and to the LCD’s back plane. When used to drive LED displays, a high is required at the Phase input for common cathode displays, while a low is required for common anode displays. To blank the display (set outputs a-g low), the BL input is set high. The CD4543B also comes with a Latch Disable input (LD), which can be used to latch onto input data, preventing new input data from altering the display.


FIGURE 12.135


The MM5453 (National Semiconductor) is a 40-pin IC that can drive up to 33 segments of an LCD, which can be used to drive 4½-digit seven-segment displays. It houses an internal oscillator section (requiring an external RC circuit) that generates the necessary squarewaves used to drive the LCD. To activate given segments within the display, a serial code is applied to the data input. The code first starts out with a start bit (high) followed by data bits that specify which outputs should be driven high or low. Figure 12.136 shows an example display circuit, along with corresponding data format required to drive a 4½-digit display.


FIGURE 12.136


FIGURE 12.137


There are a number of specialized LCDs that can be found in the electronics catalogs. An example is Varitronix’s VI-322-DP 3½-digit (plus ∼, +, BAT, Δ) LCD, shown in Fig. 12.136. This display is configured in a static drive arrangement (each segment has a separate lead) and is found in many test instruments. To drive this display, you first check to see what kind of driver the manufacturer suggests. In this case, the manufacturer suggests using Intersil’s ICL7106. This IC is a 3½-digit LCD/LED display driver as well as an ADC. This dual-purpose feature makes it easy to interface transducers directly to the same IC that is driving the display. To learn how to use the ICL7106, check out Intersil’s data sheet at

Multiplexed LCDs

We have just seen examples of static-drive-type LCDs, where each segment (to electrode) had its own lead, and a single common plane was used as the back electrode. Another type of LCD is designed with multiplexing in mind and is referred to as dynamic drive or multiplexed display.

As with the multiplexed LED display, multiplexed LCDs can greatly reduce the number of external connections required between the display and driver. However, they require increased complexity in drive circuitry (or software) to drive. In a multiplexed LCD, appropriate segments are connected together to form groups that are sequentially addressed by means of multiple back-plane electrodes.

“Intelligent” Dot-Matrix LCD Modules

Dot-matrix LCDs are used to display alphanumeric characters and other symbols. These displays are used in cell phones, calculators, vending machines, and many other devices that provide the user with simple textual information. Dot-matrix LCDs are also used in laptop computer screens; however, these displays incorporate special filters, multicolor back lighting, and so on. For practical purposes, we’ll concentrate on the simple alphanumeric LCDs.

An alphanumeric LCD screen is usually divided into a number of 5 × 8 pixel blocks, with vertical and horizontal spaces separating each block. Figure 12.138 shows a display with 20 columns and 4 rows of 5 × 8 pixel blocks. Other standard configurations come with 8, 16, 20, 24, 32, or 40 columns and 1, 2, or 4 rows. To generate a character within a given block requires that each pixel within the block be turned on or off. As you can imagine, to control so many different pixels (electrode segments) requires a great deal of sophistication. For this reason, an intelligent driver IC is required.


FIGURE 12.138

Almost all alphanumeric LCD modules are controlled by Hitachi’s HD44780 (or equivalent) driver IC. This driver contains the following:

· A permanent memory (CG ROM) that stores 192 alphanumeric characters

· A random access memory (DD RAM) used to store the display’s contents

· A second random access memory (CG RAM) used to hold custom symbols

· Input lines for data and instruction control signals

· Multiplexed outputs for driving LCD pixels

· Additional outputs for communicating with expansion chips to drive more LCD pixels

This driver is built right into the LCD module. (You could attempt to construct your own module by interfacing the driver with an LCD, but it would not be worth the effort—the numerous tiny connections would drive you nuts.) From now on, all modules described in this section are assumed to be HD44780-driven.


The standard LCD module comes with a 14-pin interface: eight data lines (D0-D7), three control lines (RS, W/R, and E), and three power lines (VDD, VSS, and VEE).

VDD (pin 2) and VSS (pin 1) are the module’s positive and negative power supply leads. Usually, VDD is set to +5 V, while VSS is grounded. VEE (pin 3) is the display’s contrast control. By changing the voltage applied to this lead, the contrast of the display increases or decreases. A potentiometer placed between supply voltages, with its wiper connected to VEE, allows for manual adjustment.

D0-D7 (pins 7-14) are the data bus lines. Data can be transferred to and from the display either as a single 8-bit byte or as two 4-bit nibbles. In the latter case, only the upper four data lines (D4-D7) are used.

RS (pin 4) is the Register Select line. When this line is low, data bytes transferred to the display module are interpreted as commands, and data bytes read from the display module indicate its status. When the RS line is set high, character data can be transferred to and from the display module.

R/W (pin 5) is the Read/Write control line. To write commands or character data to the module, R/W is set low. To read character data or status information from the module, R/W is set high.

E (pin 6) is the Enable control input, which is used to initiate the actual transfer of command or character data to and from the module. When writing to the display, data on the D0-D7 lines is transferred to the display when the enable input receives a high-to-low transition. When reading from the display, data become available to the D0-D7 lines shortly after a low-to-high transition occurs at the enable input and will remain available until the signal goes low again.

Figure 12.139 shows the instruction set and standard set of characters for an LCD module. Next, we’ll go through some examples illustrating how to use the instructions and how to write characters to the display.


FIGURE 12.139


Figure 12.140 shows a simple test circuit that is quite useful for learning how to send commands and character data to the LCD module. (In reality, the LCD module is connected to a microprocessor or microcontroller, as shown to the left in the figure.) In this circuit, switches connected to data inputs use pullup resistors in order to supply a high (1) when the switch is open or supply a low (0) when the switch is closed.


FIGURE 12.140

The enable input receives its high and low levels from a debounced toggle switch. Debouncing the enable switch prevents the likelihood of multiple enable signals being generated. Multiple enable signals tend to create unwanted effects, such as generating the same character over and over again across the display. The 5-kΩ pot is used for contrast. Note that in this circuit, we’ve grounded the R/W line, which means we’ll only deal with writing to the display.


When power is first applied to the display, the display module resets itself to its initial settings. Initial settings are indicated in the LCD instruction set with an asterisk. As indicated, the display is actually turned off during the initial setting condition. If we attempt to write character data to the display now, nothing will show up. In order to show something, we must issue a command to the module telling it to turn on its display.

According to the instruction set, the Display & Cursor On/Off instruction can be used to turn on the display. At the same time, this instruction also selects the cursor style. For example, if we apply the command code 0000 1111 to D7-D0, making sure to keep RS low so the module will interpret data as a command, a blinking cursor with an underline should appear at the top leftmost position on the display. But before this command can take effect, it must be sent to the module by momentarily setting the Enable (E) line low.

Another important instruction that should be implemented after power-up is the Function Set command. When a two-line display is used, this command tells the module to turn on the second line. It also tells the module what kind of data transfer is going to be used (8-bit or 4-bit), and whether a 5 × 10 or 5 × 7 pixel format will be used (5 × 10 is found in some one-line displays). Assuming that the display used in our example circuit is a two-line display, we can send the command 0011 1000 telling the display to turn on both lines, use an 8-bit transfer, and provide a 5 × 7 pixel character format. Again, to send this command, we set RS low, then supply the command data to D7-D0, and finally pulse E low.

Now that the module knows what format to use, we can try writing a character to the display. To do this, we set the module to character mode by setting RS high. Next, we apply one of the 8-bit codes listed in the standard LCD character set table to the data inputs D7-D0. For example, if we want to display the letter Q, we apply 01010001 (hex 51 or 51H). To send the character data to the LCD module, we pulse E low. A Q should then appear on the display. To clear the screen, we use the Clear Display command 0000 0001, remembering to keep RS low and then pulsing E low.


After power-up, the module’s cursor is positioned at the far-left corner of the first line of the display. This display location is assigned a hexadecimal address of 00H. As new characters are entered, the cursor automatically moves to the right to a new address of 01H, then 02H, and so on. Although this automatic incrementing feature makes life easy when entering characters, there are times when it is necessary to set the cursor position to a location other than the first address location.

To set the cursor to another address location, a new starting address must be entered as a command. There are 128 different addresses to choose from, although not all these addresses have their own display location. In fact, there are only 80 display locations laid out on a single line in one-line mode or 40 display locations laid out on each line in two-line mode. Now, as it turns out, not all display locations are necessarily visible on the screen at one time. This will be made more apparent in a moment. Let’s first try a simple address example with the LCD module set to two-line mode (provided that two lines are actually available).

To position the cursor to a desired location, we use the Set Address command. This command is specified with the binary code 1000 0000 + (binary value of desired hex address). For example, to send a command telling the cursor to jump to the 07H address location, we apply (1000 0000 + 0000 0111) = 1000 0111 to the D7-D0 inputs, remembering to hold RS low and then pulsing E low. The cursor should now be located at the eighth position over from the left.

It is important to realize that the relationship between addresses and display locations varies from module to module. Most displays are configured with two lines of characters, with the first line starting at address 00H and the second line at address 40H. Figure 12.141 shows the relationship between the address and display locations for various LCD modules. Note that the four-line module is really a two-line type with the two lines split, as shown in the figure.


FIGURE 12.141


Regardless of their size, LCD modules have 80 display locations that can be written to. With smaller displays, not all 80 locations can be displayed at once on the screen. For example, if we were to enter all the letters of the alphabet onto the first line of a 20-character display, only letters A through T would appear on the screen. Letters S through Z, along with the cursor, would be “pushed off” to the right of the screen, hidden from view.

To bring these hidden characters into view, we can apply the Cursor/Display Shift command to shift all display locations to the left. The command for shifting to the left is 0001 1000. Every time this command is issued, the characters shift one step to the left. In our example, it would take seven of these commands to bring T through Z and the cursor into view.

To shift things to the right, we apply the command 0001 1100. To bring the cursor back to address 00H and shift the display address 00H back to the left-hand side of the display, a Cursor Home command (0000 0010) can be issued. Another alternative is to use the Clear Display command 0000 0001. However, this command also clears all display locations.


If you do not want to enter characters from left to right, you can use the Character Entry Mode command to enter characters from right to left. To do this, the cursor must first be sent to the rightmost display location on the screen. After that, the Character Entry Mode command 0000 0111 is entered into the module. This sets the entry mode to autoincrement/display shift left. Now, when characters are entered, they appear on the right-hand side, while the display shifts left for each character entered.


Commands 0100 0000 to 0111 1111 are used to program user-defined graphics. To program these graphics on-screen, the display is cleared, and the module is sent a Set Display Address command to position the cursor at address 00H. At this point, the contents of the eight user character locations can be viewed by entering binary data 0000 0000 to 0000 0111 in sequence. These characters will appear initially as garbage.

To start defining the user-defined graphics, a Set CGRAM command is sent to the module. Any value between 0100 0000 (40H) and 0111 1111 (7F) will work. Data entered from now on will be used to construct the user-defined graph, row by row. For example, to create a light bulb, the following data entries are made: 0000 1110, 0001 0001, 0001 0001, 0001 0001, 0000 1110, 0000 1010, 0000 1110, 0000 0100. Notice that the first three most significant bits are always 0 because there are only 5 pixels per row. Other user-defined graphics can be defined by entering the 8-byte sequence, and so on. Figure 12.142 shows how the CGRAM address corresponds to the individual pixels of the user-defined graphic.


FIGURE 12.142

There are up to eight user-defined graphics that can be programmed. These then become part of the character set and can be displayed by using codes 0000 0000 to 0000 1111 or 0000 1000 to 0000 1111, both of which produce the same result.

One problem when creating user-defined graphics is they will be lost when power is removed from the module—a result of the volatile CGRAM. Typically, the user-defined graphic data is actually stored in an external nonvolatile EPROM or EEPROM, where the data is copied by a microprocessor and loaded into the display module sometime after power-up.


As indicated in the Function Set command, the LCD module is capable of both 8-bit and 4-bit data transfer. In 4-bit mode, only data lines D4-D7 are used. The other four lines, D0-D3, are left either floating or tied to the power supply. To send data to the display requires sending two 4-bit chunks instead of one 8-bit word.

When power is first applied, the module is set up for 8-bit transfer. To set up 4-bit transfer, the Function Set command with binary value 0010 0000 is sent to the display. Note that since there are only four data lines in use, all 8 bits cannot be sent. However, this is not a problem, since the 8-bit/4-bit selection is on data bit D4. From now on, 8-bit character and command bits must be sent in two halves, the first 4 most significant bits and then the remaining 4 bits. For example, to write character data 0100 1110 to the display requires setting RS high, applying 0100 to the data lines, pulsing E low, then applying 1110 to the data lines, and pulsing E low again.

The 4-bit transfer is frequently used when the LCD module is interfaced with a microcontroller that has limited I/O lines. See Fig. 12.142.

12.11 Memory Devices

Memory devices provide a means of storing data on a temporary or permanent basis for future recall. The storage medium used in a memory device may be a semiconductor-based IC (primary memory), a magnetic tape, a magnetic disk, or an optical disk (secondary memories). In most cases, the secondary memories are capable of storing more data than primary memories because their surface areas are larger. However, secondary memories take much longer to access (read or write) data because memory locations on a disk or tape must be physically positioned to the point where they can be read or written to by the read/write mechanism. Within a primary memory device, memory locations are arranged in tiny regions within a large matrix, where each memory location can be accessed quickly (matter of nanoseconds) by applying the proper address signals to the rows within the matrix.

Figure 12.143 shows an overview of primary and secondary memories. In this section, we’ll discuss only the primary memories, since these devices are used more frequently in designing gadgets than secondary memories. Secondary memories are almost exclusively used for storing large amounts of computer data, audio data, or video data.


FIGURE 12.143

Today, the technology used in the construction of primary memory devices is almost exclusively based on MOSFET transistors. Bipolar transistors are also used within memory ICs. However, these devices are less popular because the amount of data they can store is significantly smaller than that of a memory IC built with MOSFET transistors. At one time, bipolar memories had a significant edge in speed over MOSFET memories, but today the speed gap has almost disappeared.

Memory devices consist of two basic subfamilies: read-only memory (ROM) and read/write memory (RWM), which is more commonly referred to as random-access memory (RAM). Within each of these subfamilies exist more subfamilies, as shown in Fig. 12.143. Let’s start out by discussing the ROM devices.

12.11.1 Read-Only Memory

ROM is used to store data on a permanent basis. These devices are capable of random access, like RAM devices, but unlike RAM devices, they do not lose stored data when power is removed from the IC.

ROM is used in nearly all computers to store boot-up instructions (such as stack allocation, port and interrupt initializations, and instructions for retrieving the operating system from disk storage) that are enacted when the computer is first turned on.

In some microcontroller applications (simple-function gadgets, appliances, toys, and so on), the entire stand-alone program resides in ROM. The microcontroller’s central processing unit (CPU) retrieves the program instructions and uses volatile RAM for temporary data storage as it runs through the ROM’s stored instructions.

In some instances, you find ROM within discrete digital hardware, where it is used to store lookup tables or special code-conversion routines. For example, digital data from an ADC could be used to address stored words that represent, say, a binary equivalent to a temperature reading in Celsius or Fahrenheit. This also can be used to replace a complex logic circuit, where, instead of using a large number of discrete gates to get the desired function table, you simply program the ROM to provide the designed output response when input data is applied. The last few applications mentioned, however, are becoming a bit obsolete—the microcontroller seems to be taking over everything.

ROM is generally used for read-only operations and not written to after initially programmed. However, some ROM-like devices, such as EPROM, EEPROM, and flash memory, are capable of erasing stored data and rewriting data to memory. Before we take a look at these erasable ROM-like devices, let’s first cover some memory basics.

12.11.2 Simple ROM Made Using Diodes

To get a general idea of how ROM works, let’s consider the simple circuit in Fig. 12.144.


FIGURE 12.144

This is a simple ROM device that uses an address decoder IC to access eight different 4-bit words stored in a diode matrix. Data to be read is output via the D3-D0 lines. The diode matrix is broken up into rows and columns. The intersection of a row and column represents a bit location. When a given row and column are linked together with a diode, the corresponding data output line goes low (0) when the corresponding column is selected by the address decoder via the A2-A0 inputs. When a specific row is addressed, the NAND gate sinks current, so the current from the supply passes through the diode and into the NAND gate’s output. This makes the corresponding data line low. When no diode is placed between a given column and row, the corresponding data line goes high (0) when the corresponding row is selected by the address decoder. (There is no path to ground in this case.) In this particular example, we have an 8 × 4 ROM (eight different 4-bit words). By increasing the width of the matrix (adding more columns), it is possible to increase the word size. By increasing the height of the matrix (adding more rows—more addresses), it is possible to store more words. In other words, we could make an m × n ROM.

In reality, today’s ROM devices rarely use diode memory cells. Instead, they typically use transistor-like memory cells formed on silicon wafers. Also, a more realistic ROM device comes with three-state output buffers that can be enabled or disabled (placed in a high Z state) by applying a control signal. The three-state buffers make it possible to effectively disconnect the memory from a data bus to which it is attached. (In our simple diode memory circuit, the data is always present on the output lines.) The basic layout, with address decoder and memory cells, is pretty much the same for all memory devices. There are additional features, however, and we’ll discuss these in a minute. First, let’s cover some memory nomenclature.

12.11.3 Memory Size and Organization

A ROM that is organized in an n × m matrix can store n different m-bit words; in other words, it can store n × m bits of information. To access n different words requires log2n address lines. For example, our simple ROM in Fig. 12.144 requires log2 8 = 3 address inputs (this may look more familiar: 23 = 8). Note that within multiplexed memories and memories that come with serial inputs, the actual physical number of address inputs is ether reduced or the address information is entered serially, along with data and other protocol information.

In terms of real memory ICs, the number of address inputs is typically eight or higher (for parallel input devices at any rate). Common memory sizes are indicated in Table 12.2. Note that in the table, 1K is used to represent 1024 bits, not 1000 bits, as the k (kilo) would lead you to believe. By digital convention, we say that 21 = 2, 22 = 4, 23 = 8, … 28 = 256, 29 = 512, 210 = 1,024 (or 1 K), 211 = 2,048 (or 2 K), … 218 = 262,144 (256K), 219 = 524,288 (540 K), 220 = 1,048,576 (or 1 M, for mega), 221 = 2,097,152 (2 M), … 230 = 1,073,741,824 (or 1 G, for giga), and so on.

TABLE 12.2 Common Memory Sizes










16,384 (16 K)


1,048,576 (1 M)




32,768 (32 K)


2,097,152 (2 M)


1,024 (1 K)


65,536 (64 K)


4,194,304 (4 M)


2,048 (2 K)


131,072 (128 K)


8,388,608 (8 M)


4,096 (4 K)


262,144 (256 K)


16,777,216 (16 M)


8,192 (8 K)


524,288 (540 K)


33,554,432 (32 M)

If this convention confuses you, it should. It is not exactly obvious, and leaves you scratching your head. Also, when a data sheet says 64 K, you need to read further to figure out what the actual organization is, say, 2048 × 32 (2 K × 32), 4096 × 16 (4 K × 16), 8192 × 8 (8 K × 8), 16,384 × 4 (16 K × 4), or another system.

In Table 12.2, watch out for terms such as kB, MB, and GB. These terms refer to bytes not bits; the B signifies 1 byte, or 8 bits. This means that a memory that stores 1 kB actually stores 1 K × 8 (8 K) bits of data. Likewise, memories that store 1 MB and 1 GB actually store 1 M × 8 (8 M) and 1 G × 8 (8 G) bits of data, respectively.

12.11.4 Simple Programmable ROM

Figure 12.145 shows a more accurate representation of ROM-type memory. Unlike the diode ROM, each memory cell contains a transistor and fusible link. Initially, the ROM has all programmable links in place. With every programmable link in place, every transistor is biased on, causing high voltage levels (logic 1s) to be stored throughout the array. When a programmable link is broken, the corresponding memory cell’s transistor turns off, and the cell stores a low voltage level (logic 0). Note that this ROM contains three-state output buffers that keep the output floating until a low is applied to the Chip Enable input. This feature allows the ROM to be interfaced with a data bus.


FIGURE 12.145

A basic ROM circuit schematic is shown in Fig. 12.145, along with the appropriate address and chip-enable waveforms needed to enact a read operation. To read data stored at a given address location, the Chip Enable input is set high to disable the chip (remove old data from data outputs)—see time t0. At time t1, a new address is placed on the 3-bit address bus (A2, A1, and A0). At time t2, the Chip Enable input is set low, which allows addressed data stored in memory to be output via D3, D2, D1, and D0.

In reality, the stored data is not output immediately but is delayed for a very short time (from t2 to t3) due to the propagation delay that exists between the initial chip enable signal and the signal that reaches the enable leads of the output buffers. In memory lingo, the time from t1 to t4 is referred to as the access time, which is between around 10 ns and a couple hundred nanoseconds, depending on the specific technology used.

Now two important questions need addressing:

· How does one “break” a programmable link? In other words, how do we program the ROM?

· Is it possible to restore a broken programmable link back to its unbroken” state? In other words, is it possible to reprogram the ROM?

These lead to the next topic.

12.11.5 ROM Devices

There are basically two kinds of ROMs: those that can be programmed only once and those that can be reprogrammed any number of times. One-time programmable memories include the mask ROM (MROM) and the programmable ROM (PROM). ROMs that can be reprogrammed include the erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.


An MROM is a custom memory device that is permanently programmed by the manufacturer simply by adding or leaving out diodes or transistors within a memory matrix. In order to create a desired memory configuration, you must supply the manufacturer with a truth table stating which data configuration is desired. Using the truth table, the manufacturer then generates a mask that is used to create the interconnections within the memory matrix during the fabrication process.

As you can imagine, producing a custom MROM is not exactly cheap; in fact, it is rather costly (more than $1,000). It is only worthwhile using an MROM if you plan to mass produce some device that requires the same data instructions (for example, program instructions) over and over again—no upgrades to memory needed in the future. In this case, the cost for each IC—after the initial mask is made—is relatively cheap, assuming you need more than a couple thousand chips.

MROMs are commonly found in computers, where they are used to store system operating instructions and data that is used to decode keyboard instructions.


PROMs are fusible-link programmable ROMs. Unlike the MROM, with PROM devices, data is not etched in stone. Instead, the manufacturers provide you with a memory IC whose matrix is clean (full of 1s). The number of bits and the configuration (n × m) of the matrix vary depending on specific ROM. To program the memory, each fusible link must be blown with a high-voltage pulse (such as 21 V).

The actual process of blowing individual fuses requires a PROM programming unit. This PROM programmer typically includes a hardware unit (where the actual PROM IC is attached), along with programming cable that is linked to a computer (such as via a serial or parallel port). Using software provided by the manufacturer, you enter the desired memory configuration in the program running on the computer and then press a key, which causes the software program to instruct the external programming unit to blow the appropriate links within the IC.

PROMs are relatively easy to program once you have figured out how to use the software, but as with MROMs, once the device is programmed; the memory cannot be altered. In other words, if you mess things up, you must begin afresh with a new chip. These devices were popular some years ago, but today they are considered obsolete.

The most popular ROM-type devices used today are EPROM, EEPROM, and flash memory. These devices, unlike MROM and PROM devices, can be erased and reprogrammed—a very useful feature when prototyping or designing a gadget that requires future memory alterations.


An EPROM is a device whose memory matrix consists of a number of specialized MOSFET transistors. Unlike a conventional MOSFET transistor, the EPROM transistor has an additional floating gate that is buried beneath the control gate—insulated from both the control gate and drain-to-source channel by an oxide layer (see Fig. 12.146).


FIGURE 12.146

In its erased (unprogrammed) state, the floating gate is uncharged and does not affect the normal operation of the control gate (which when addressed results in a high voltage or logic 1 being passed through to the data lines). To program an individual transistor, a high-voltage pulse (around 12 V) is applied between the control gate and the drain terminal. This pulse, in turn, forces energetic electrons through the insulating layer and onto the floating gate (referred to as hot electron injection). After the high voltage is removed, a negative charge remains on the floating gate and will stay there for decades under normal operating conditions.

With the negative charge in place, the normal operation of the control gate is inhibited; when the control gate is addressed, the charge on the floating gate prevents a high voltage from reaching the data line—the addressed data appears as a low, or logic 0.

In order to reprogram (erase) an EPROM, you must first remove the device from the circuit and then remove a sticker covering its quartz window. After that, you remove all stored charges on the floating gates by shining ultraviolet (UV) light through the window onto the interior transistor matrix. The UV light liberates the stored electrons within the floating gate region by supplying them with enough energy to force them through the insulation. It usually takes 20 minutes of UV exposure for the whole memory matrix to be erased. The number of times an EPROM can be reprogrammed is typically limited to a couple hundred cycles. After that, the chip degrades considerably.

EPROM is often used as nonvolatile memory within microprocessor-based devices that require the provision for future reprogramming. They are frequently used in prototyping and then substituted with MROMs during the mass-production phase. EPROMs are also integrated within microcontroller chips where their sole purpose is to store the microcontroller’s main program (more on this in Chap. 13).


An EEPROM device uses a technology somewhat related to the EPROM, but it does not require out-of-circuit programming or UV erasing. Instead, an EEPROM device is capable of selective memory cell erasure by means of controlled electrical pulses.

In terms of architecture, an EEPROM memory cell consists of two transistors: one transistor resembles the EPROM transistor and is used to store data, and the other transistor is used to clear charge from the first transistor’s floating gate. By supplying the appropriate voltage level to the second transistor, it is possible to selectively erase individual memory cells instead of having to erase the entire memory matrix, as is the case with EPROM. The only major disadvantage with EEPROM over EPROM is size—due to the two transistors. However, today, with the introduction of new fabrication processes, size is becoming less of an issue.

In terms of applications, EEPROM is ideal for remembering configuration and calibration settings of a device when the power is turned off. For example, EEPROM is found within TV tuners, where it is used to remember the channel, volume setting of the audio amplifier, and so on when the TV is turned off. EEPROM is also found on microcontrollers, where it can be used to store the main program or to hold other nonvolatile data

Flash Memory

Flash memory is generally regarded as the next evolutionary step in ROM technology that combines the best features of EPROM and EEPROM. These devices have the advantage of both in-circuit programming (like EEPROM) and high storage density (like EPROM).

Some variants of flash memory are electrically erasable, like EEPROM, but must be erased and reprogrammed on a device-wide basis, similar to EPROM. Other devices are based on a dual transistor cell and can be erased and reprogrammed on a word-by-word basis. Flash devices are noted for their fast write and erase times, which exceed those of EEPROM devices.

Flash memories are becoming very popular as mass-storage devices. They are found in digital cameras, where a high-capacity flash memory card is inserted directly into a digital camera and can store hundreds or thousands of high-resolution images. They are also used in digital music players, cellular phones, tablets, and so on.

Microcontrollers often include flash memory to contain their program.

Serial Access Memory

So far, we have seen only memories that incorporated parallel access. These devices sit directly on the address and data buses, making it easy for processors to quickly access the memory. Serial access memory is easy to use in principle; however, since all their address lines are typically tied to an address bus within a microprocessor-based system, it is not uncommon for the data to be inadvertently destroyed when the processor runs amuck (issues an undesired write).

Another type of memory that can “hide” the memory from the processor, as well as reduce the total number of pins, uses a serial access format. To move data to and from memory and the processor, a serial link is used. This serial link imposes a strict protocol on data transfers that practically eliminates the possibility that the processor can destroy data accidentally.

Figure 12.147 shows a few serial EPROM and EEPROM devices from Microchip. The SDA pin found in the EEPROM devices acts as a bidirection data lead used to transfer address and data information into the memory IC, as well as transfer data out to the processor. The SCL pin is the serial clock input used to synchronize the data transfer from and to the device. The 24xx64 and 24LC01B/02B EEPROMs also come with special device address inputs A0, A1, and A2, which are used for multiple device operation. WP is used to enable normal memory operation (read/write entire memory) or inhibit write operations.


FIGURE 12.147

Controlling a serial memory device is a bit complex, due to the serial protocol and variations in protocol from IC to IC. If you want to learn more about these serial memories (and you should—they are very handy in microcontroller applications for logging data and storing programs and similar tasks), check out the various manufacturers’ websites and read through their data sheets.

12.11.6 RAM

The erasable programmable ROM devices, like EEPROM, have limited read/write endurance—around 100,000 cycles—and take considerable time to write to memory. For applications that require constant and quick read and write cycles, it is necessary to use RAM. This type of memory is used for temporary storage of data and program instructions in microprocessor-based applications. Unlike ROM devices, however, RAM devices are volatile, which means they lose their data if power to the IC is interrupted.

There are two basic types of RAM:

· Static RAM (SRAM): In an SRAM device, data is stored in memory cells that consist of flip-flops. A bit that is written into an SRAM memory cell stays there until overwritten or until the power is turned off.

· Dynamic RAM (DRAM): In a DRAM device, a bit written to the memory cell will disappear within milliseconds if not refreshed, or supplied with periodic clocking to replenish capacitor charge lost to leakage.

In general, the major practical differences between SRAM and DRAM include overall size, power consumption, speed, and ease of use. In terms of size, DRAM devices can hold more data per unit area than SRAM devices, since a DRAM’s capacitor takes up less space than an SRAM’s flip-flop. In terms of power consumption, SRAMs are more energy-efficient because they do not require constant refreshing. In terms of speed and ease of use, SRAMs are superior because they do not require refresh circuitry.

In terms of applications, SRAMs are used when relatively small amounts of read/write memory are needed and are typically found within application-specific ICs that require extremely low standby power. For example, they are frequently used within portable equipment such as pocket calculators. SRAM is also integrated into all modern microprocessors, where it acts as on-chip cache memory that provides a high-speed link between the processor and memory. On the other hand, DRAM is used in applications where a large amount of read/write memory (within the megabyte range) is needed, such as within computer memory modules.

In most situations, you do not need to worry about dealing with discrete RAM memory ICs. Most of the time, RAM is already built into a microcontroller or conventionally housed on PCB memory modules that simply plug into a computer’s memory banks. In both these cases, you really do not need to know how to use the memory, because you can let the existing hardware and software take care of the addressing, refreshing, and so on. For this reason, we will not discuss the finer details of the various discrete SRAM and DRAM ICs out there. Instead, we will take a look at some SRAM and DRAM block diagrams that illustrate the basics, and then we will discuss some memory packages, such as SIMMs and DIMMs, that are used within computers.

Very Simple SRAM

Figure 12.148 shows a very elementary SRAM that is set up with a 4096 (4 K) × 1-bit matrix. It uses 12 address lines to address 4096 different memory locations; each location contains a flip-flop. The memory matrix is set up as a 64 × 64 array, with A0 to A5 identifying the row and A6 to A11 identifying the column to pinpoint the specific location to be used. The box labeled “Row Select” is a 6-to-64 decoder for identifying the appropriate 1-of-64 row. The box labeled “Column Select” is also a 6-to-64 decoder for identifying the appropriate 1-of-64 column.


FIGURE 12.148

To write a new bit of data to memory, the bit is applied to DIN, the address lines are set, the Chip Select input ( ) is set low (to enable the chip), and the Write Enable input ( ) is set low (to enable the DIN buffer). To read a bit of data from memory, the address lines are set, is set low, and is set high (to enable the DOUT buffer). See the timing waveforms in Fig. 12.148.

By combining eight 4 K × 1 SRAM ICs together, as shown in the lower circuit in Fig. 12.148, the memory can be expanded to form a 4 K × 8 configuration, which is useful in simple 8-bit microprocessor systems. When an address is applied to the address bus, the same address locations within each memory IC are accessed at the same time. Therefore, each data bit of an 8-bit word applied to the data bus is stored in the same corresponding address locations within the memory ICs.

There are other SRAM ICs that come with configurations larger than n × 1. For example, they may come in, say, an n × 4 or n × 8 configuration. As with the n × 1 devices, these SRAMs can be expanded (two n × 8 devices could be combined to form an n × 16 expanded memory, four n × 8 devices could be combined to form an n × 32 expanded memory, and so on).

Serial SRAM with a similar interface to serial EEPROM is also available. For an example of the types of serial SRAM available see

Note on Nonvolatile SRAMs

In many applications, it would be ideal to have a memory device that combines both the speed and cycle endurance of an SRAM with the nonvolatile characteristics of ROM devices. To solve this problem, manufacturers have created what are called nonvolatile SRAMs. One such device incorporates a low-power CMOS SRAM together with a lithium battery and power-sensory circuitry. When the power is removed from the chip, the battery kicks in, providing the flip-flops with sufficient voltage to keep them set (or reset). SRAMs with battery backup, however, have limited lifetimes due to the life expectancies of the lithium batteries—around ten years.

Another nonvolatile SRAM that requires no battery backup is referred to as nonvolatile RAM (NOVRAM). These chips incorporate a backup EEPROM memory array in parallel with an ordinary SRAM array. During normal operation, the SRAM array is written to and read from just like an ordinary SRAM. When the power supply voltage drops, an onboard circuit automatically senses the drop and performs a store operation that causes all data within the volatile SRAM array to be copied to the nonvolatile EEPROM array. When power to the chip is turned on, the NOVRAM automatically performs a recall operation that copies all the data from the EEPROM array back into the SRAM array. A NOVRAM has essentially unlimited read/write endurance, like a conventional SRAM, but has a limited number of store-to-EEPROM cycles—around 10,000.


Figure 12.149 shows a very basic 16 K × 1 DRAM. Normally, to access all 16,384 memory locations (capacitors) would require 14 address lines. However, in this DRAM (as within most large-scale DRAMs), the number of address lines is cut in half by multiplexing.


FIGURE 12.149

To address a given memory location is a two-step process. First, a 7-bit row address is applied to A0-A6, and then Row Address Strobe is sent low. Second, a 7-bit column address is applied to A0-A6, and then Column Address Strobe is sent low. At this point the memory location is latched and can now be read or written to by using the input. When is low, data is written to the RAM via Din. When is high, data is read from the RAM via Dout. See the timing waveforms in Fig. 12.149.

Simple DRAM devices like this must be refreshed every 2 ms or sooner to replenish the charge on the internal capacitors. For our simple device, there are three ways to refresh the cells: use a Read cycle, use a Write cycle, or use an -only cycle. Unless you are reading or writing to and from all 128 rows every 2 ms, the -only cycle is the preferred technique. To perform this cycle, is set high, A0-A6 are set up with the row address 000 0000, is pulsed low, the row address is then incremented by 1, and the last two steps are repeated until all 128 rows have been accessed.

As you can see, needing to come up with the timing waveforms to refresh the memory is a real pain. For this reason, manufacturers produce DRAM controllers or actually incorporate automatic refreshing circuitry within the DRAM IC. In other words, today’s DRAMs have all the “housekeeping” functions built in. Practically speaking, this makes the DRAM appear static to the user.

DRAM technology is changing very rapidly. Today, there are a number of DRAM-like devices that go by such names as ECC DRAM, EDO DRAM, SDRAM, SDRAM II, RDRAM, and SLDRAM (we will discuss some of these at the end of this chapter).

Computer Memory

As mentioned, you typically do not need to worry about RAM. (The only real exception would be NOVRAM that is used in many EEPROM-like applications.) RAM is usually either already integrated into a chip, such as a microcontroller, or is placed in reduced pin devices like single in-line memory modules (SIMMs) or dual in-line memory modules (DIMMs) that slide (snap) into a computer’s memory bank sockets. In both cases, not much thought is needed—assuming you are not trying to design a microcontroller or computer from scratch. The main concern nowadays is figuring out what kind of RAM module to buy for your computer.

Within computers, RAM is used to hold temporary instructions and data needed to complete tasks. This enables the computer’s CPU to access instructions and stored data in memory very quickly. For example, when the CPU loads an application, such as a word processor or page layout program, into memory, the CPU can quickly find what it needs, instead of needing to search for bits and pieces from, say, the hard drive or external drive. For RAM to be quick, it must be in direct communication with the computer’s CPU. Early on, memory was soldered directly onto the computer’s system board (motherboard). However, over time, as memory requirements increased, having fixed memory onboard became impractical. Today, computers house expansion slots arranged in memory banks. The number of memory banks and the specific configuration vary, depending of the computer’s CPU and how the CPU receives information.

Historically, computers initially used either SIMM or DIMM memory modules. Both types of modules use dynamic RAM ICs as the core element. The actual SIMM or DIMM module resembles a PCB and houses a number of RAM ICs that are expanded onboard to provide the necessary bit width required by the CPU using the module. To install a SIMM or DIMM module, simply insert the module into one of the computer memory banks sockets found on the motherboard. Many computer systems use 168-pin DIMMs. Older Pentium and later 486 PCs commonly use 72-pin SIMMs, while still older 486 PCs commonly use 30-pin SIMMs.

A variation on standard sizes of DIMM memory is the SODIMM. SODIMM (Small Outline DIMM) are electrically the same as standard DIMMs but smaller in size and intended for use in laptop computers.


DIMMs have opposing pins electrically isolated to form two separate contacts. DIMMs are often used in computer configurations that support a 64-bit or wider memory bus.

Each new generation of memory brings with it new formats of DIMM, with strategically placed slots to prevent accidental insertion of the wrong type of memory.

DDR3 memory comes in 240-pin DIMMs. Figure 12.150 shows a somewhat simpler sample package from an old 16 M × 64-bit synchronous DRAM that comes in a 168-pin DIMM package.


FIGURE 12.150

DRAM Technology Used in Computer Memories

A number of DRAM technologies are incorporated into computer memory modules these days. Extended data out (EDO) memory is a technology that allows the CPU (ones that support EDO) to access memory 10 to 20 percent faster than standard DRAM chips.

Another variation of DRAM is the synchronous DRAM (SDRAM), which uses a clock to synchronize signals input and output on a memory chip. The clock is coordinated with the CPU clock so the timing of the memory chips and the timing of the CPU are in synch. Synchronous DRAMs save time in executing commands and transmitting data, thereby increasing the overall performance of the computer. SDRAM allows the CPU to access memory approximately 25 percent faster than EDO memory.

Double-data-rate SRAM (DDR or SDRAMM II) is a faster version of SDRAM that is able to read data on both the rising and falling edges of the system clock, thus doubling the data rate of the memory chip. Rambus DRAM (RDRAM) is an extremely fast DRAM technology that uses a high-bandwidth “channel” to transmit data at speeds about ten times faster than a standard DRAM.